PI2EQX5864 Datasheet, PDF (14/18 Pages) Pericom Semiconductor Corporation – 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis, &I2C Control

PI2EQX5864
5.0Gbps 4-Lane PCI Express GenII Re-Driver
with Equalization, Emphasis and I²C Control
SDA and SCL I/O for I2C-bus (V_DD = 1.2 ± 0.05v, T_A = 0 to 70°C)
Symbol Parameter
Conditions
V_IH
DC input logic high
V_IL
DC input logic low
V_OL
DC output logic low
I_OL = 3mA
V_hys
Hysteresis of Schmitt trigger input
Min.
1.1
-0.3
0.2
Typ.
Max.
Units
3.6
V
0.7
V
0.4
V
V
Characteristics of the SDA and SCL bus lines for F/S-mode I2C-bus devices⁽¹⁾
Symbol
Parameter
Conditions
Min.
f_SCL SCL clock frequency
0
t_HD;STA Hold time (repeated) START condition. After
4.0
this period, the first clock pulse is generated
t_LOW LOW period of the SCL clock
4.7
t_HIGH HIGH period of the SCL clock
4.0
t_SU;STA Set-up time for a repeated START condition
4.7
t_HD;DAT Data hold time
5.0
t_SU;DAT Data set-up time
250
t_r
Rise time of both SDA and SCL signals
–
t_f
Fall time of both SDA and SCL signals
t_SU;STO Set-up time for STOP condition
4.0
t_BUF Buss free time between a STOP and STOP
4.7
condition
C_b Capacitive load for each bus line
–
Typ.
Max.
Unit
100
kHz
–
μs
–
μs
–
μs
–
μs
–
μs
–
ns
100
ns
300
ns
–
μs
–
μs
400
pF
Notes:
1. All values referred to V_IHmin and V_ILmax levels.
2. A device must initially provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
07-0277
14
PS8934A
01/21/08