PI2EQX5864 Datasheet, PDF (2/18 Pages) Pericom Semiconductor Corporation – 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis, &I2C Control

Pin Description
Pin #
Data Signals
2
3
48
47
7
8
43
42
12
13
38
47
17
18
33
32
46
45
4
5
41
40
9
10
36
35
14
15
31
30
19
20
Control Signals
26, 27, 25
28
23
51
PI2EQX5864
5.0Gbps 4-Lane PCI Express GenII Re-Driver
with Equalization, Emphasis and I²C Control
Pin Name Type Description
A0RX+,
I
A0RX-
I
A0TX+,
O
A0TX-
O
A1RX+,
I
A1RX-
I
A1TX+,
O
A1TX-
O
A2RX+,
I
A2RX-
I
A2TX+,
O
A2TX-
O
A3RX+,
I
A3RX-
I
A3TX+,
O
A3TX-
O
B0RX+,
I
B0RX-
I
B0TX+,
O
B0TX-
O
B1RX+,
I
B1RX-
I
B1TX+,
O
B1TX-
O
B2RX+,
I
B2RX-
I
B2TX+,
O
B2TX-
O
B3RX+,
I
B3RX-
I
B3TX+,
O
B3TX-
O
CML inputs for Channel A0, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A0, with internal 50-Ohm pull up during normal opera-
tion and 2K-Ohm pull up otherwise.
CML inputs for Channel A1, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A1, with internal 50-Ohm pull up during normal opera-
tion and 2K-Ohm pull up otherwise.
CML inputs for Channel A2, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A2, with internal 50-Ohm pull up during normal opera-
tion and 2K-Ohm pull up otherwise.
CML inputs for Channel A3 with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel A3, with internal 50-Ohm pull up during normal opera-
tion and and 2K-Ohm pull up otherwise.
CML inputs for Channel B0, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B0, with internal 50-Ohm pull up during normal opera-
tion and 2K-Ohm pull up otherwise.
CML inputs for Channel B1, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B1, with internal 50-Ohm pull up during normal opera-
tion and 2K-Ohm pull up otherwise.
CML inputs for Channel B2, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B2, with internal 50-Ohm pull up during normal opera-
tion and 2K-Ohm pull up otherwise.
CML inputs for Channel B3, with internal 50-Ohm pull down during normal
operation, and >200K-Ohm otherwise.
CML outputs for Channel B3, with internal 50-Ohm pull up during normal opera-
tion and 2K-Ohm pull up otherwise.
A0, A1, A4 I
LB#
I
Mode
I
PRSNT2# I
I2C programmable address bit A0, A1 and A4.
Loopback control input. Input with innernal 100K-Ohm oull-up resistor. LB#
= High or open for normal operation. LB# = Low for loopback connection of
A_RX to A_TX and B_TX.
Enables I2C control when LOW. Has internal 100K-Ohm pull-up resistor. A
LVCMOS high level selects input pins control, and disables I²C operation. Note,
during startup, input status of the control pin (LB#, RES_A/B#, RXD_A/B) will
be latched to set the initial register state.
Input with internal 100K-Ohm pull-up resistor, card present is an active low
signal to indicate the existence of a receiver, and will enable all channels, need to
tie low for normal operation.
(Continued on Next Page)
07-0277
2
PS8934A
01/21/08