PI2EQX5864 Datasheet, PDF (8/18 Pages) Pericom Semiconductor Corporation – 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis, &I2C Control

PI2EQX5864
5.0Gbps 4-Lane PCI Express GenII Re-Driver
with Equalization, Emphasis and I²C Control
Byte 2 - Loopback and Emphasis Control Register (LBEC)
LB_xyxy#=0=loopback mode, LB_xyxy#=1=normal mode, DE_x=0=pre-emphasis, DE_x=1=de-emphasis
Bit
7
6
5
4
3
2
1
0
Name
LB_A0B0# LB_A1B1# LB_A2B2# LB_A3B3#
DE_A DE_B
rsvd
rsvd
Type
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Power-on
LB#
LB#
LB#
State
LB#
1
1
X
X
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
Individual control for each lane is provided for the loopback function via this register.
BYTE 3 - Channel Input Disable (INDIS)
INDIS_xy=0=enable input, INDIS_xy=1=disable input
Bit
7
6
5
Name INDIS_A0 INDIS_B0 INDIS_A1
4
INDIS_B1
3
INDIS_A2
2
INDIS_B2
Type
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
0
0
0
0
0
0
State
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
1
INDIS_A3
R/W
0
0
INDIS_
B3
R/W
0
The Channel Input Disable register, provides control over the input buffer of each channel independently. When and INDIS_xy bit is
logic 1, then the input buffer is switched off and the input termination is high impedance. This feature can be used for PCB testing,
and when only one input is used during Loopback as a demux function. When INDIS_xy is at a logic 0 state then the input buffer is
enabled (normal operating mode).
BYTE 4 - Channel Output Disable (OUTDIS)
ODIS_xy=0=enable output, ODIS_xy=1=disable output
Bit
7
6
5
Name
ODIS_A0
ODIS_B0 ODIS_A1
4
ODIS_B1
3
2
ODIS_A2 ODIS_B2
Type
R/W
R/W
R/W
R/W
R/W
R/W
Power-on
0
0
0
0
0
0
State
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
1
ODIS_
A3
R/W
0
0
ODIS_
B3
R/W
0
The Channel Output Disable register, allows control over the output buffer of each channel independently. When and OUTDIS_xy
bit is logic 1, then the output buffer is switched off and the termination is high impedance. This feature can be used for PCB testing,
and when only one output is used during Loopback as a mux function. When INDIS_xy is at a logic 0 state then the input buffer is
enabled (normal operating mode).
07-0277
8
PS8934A
01/21/08