PI2EQX5864 Datasheet, PDF (7/18 Pages) Pericom Semiconductor Corporation – 5.0Gbps 4-Lane PCI Express GenII Re-Driver with Equalization, Emphasis, &I2C Control

PI2EQX5864
5.0Gbps 4-Lane PCI Express GenII Re-Driver
with Equalization, Emphasis and I²C Control
Configuration Register Summary
Byte Mnemonic Function
0 SIG
Signal Detect, indicates valid input signal level
1 RX50
Receiver Detect Output, indicates whether a receiver load was detected
2 LBEC
Loopback and Emphasis Control, provides for control of the loopback function and emphasis mode (pre-
emphasis or de-emphasis)
3 INDIS
Channel Input Disable, controls whether s channels input buffer is enabled or disabled
4
OUTDIS
Channel Output Disable: Controls whether a channels output buffer is enabled or disabled
5 RESET
Channel Reset
6 PWR
Power Down Control, enables power down for each channel individually
7 RXDE
Receiver Detect Enable, controls the receiver detect operation
8 AEOC
A-Channels Equalizer and Output Control
9 BEOC
B-Channels Equalizer and Output Control
10 RSVD
Reserved
11 RSVD
Reserved
Register Description
Byte 0 - Signal Detect (SIG)
SIG_xy=0=low input signal, SIG_xy=1=valid input signal
Bit
7
6
5
Name
SIG_A0 SIG_B0
SIG_A1
4
SIG_B1
3
SIG_A2
2
SIG_B2
Type
R
R
R
R
R
R
Power-on
X
X
X
X
X
X
State
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
1
SIG_A3
R
X
0
SIG_B3
R
X
The Signal Detect register provides information on the instantaneous status of the channel input from the Input Level Threshold
Detect circuit. If the input level falls below the Vth- level the relevant SIG_xy bit will be 0, indicating a low-level noise or electri-
cal idle input, resulting in the outputs going to the high-impedance off state or squelch mode. If the input level is above Vth-, then
SIG_xy is 1, indicating a valid input signal, and active signal recovery operation.
Byte 1 - Receiver Detect Output Register (RX50)
RX50_xy = 1 = load detected, RX50_xy = 0 = No reciever found
Bit
7
6
5
4
3
2
1
0
Name RX50_A0 RX50_B0 RX50_A1 RX50_B1 RX50_A2 RX50_B2 RX50_A3 RX50_B3
Type
R
R
R
R
R
R
R
R
Power-on
X
X
X
X
X
X
X
X
State
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The RX50_xy bits report the result of a receiver detection cycle. One bit is assigned for each channel of the device. RX50_xy is
at a logic 1 level indicating a load and receiver was detected. When RX50_xy is 0 then a load device was not detected. The RX50
register is read-only, and is undefined after power-up until a Receiver Detection cycle completes.
07-0277
7
PS8934A
01/21/08