MN673794 Datasheet, PDF (4/42 Pages) Panasonic Semiconductor – LSI FOR MPEG

MN673794
Table 2.2 Pin Descriptions (2/4)
Pin No. Pin name
I/O
Voltage
Type
Drive
Function
Clock BST
53 AVDD6
Power supply 3.3 V Analog
- A/D (C) use
-
-
54 CIN
I
- Analog
- C input (analog)
27 MHz -
55 AVSS6
GND
-
-
- A/D (C) use
-
-
56 VREFLC
I
- Analog
- A/D (C) reference voltage low-level input
-
-
57 VREFMLC
58 VREFMC
59 VREFHMC
I
- _Analog
I
- Analog
I
- Analog
- ^{A/D (C) intermediate reference potential input (Capacitance coupling}
-
-
to AVSS)
A/D (C) intermediate reference potential input (Capacitance coupling
-
-
-
to AVSS)
- ^{A/D (C) intermediate reference potential input (Capacitance coupling}
-
-
to AVSS)
60 VREFHC
I
- Analog
- A/D (C) reference voltage high-level input
-
-
61 AVSS7
GND
-
-
- A/D (C) use
-
-
62 AVDD7
Power supply 3.3 V Analog
- A/D (C) use
-
-
63 AVDD8
Power supply 3.3 V
-
- A/D (Y and composite) use
-
-
64 VIDEO
I
- Analog
- Composite video input (analog)
27 MHz -
65 AVSS8
GND
-
-
- A/D (Y and composite) use
-
-
66 VREFLY
I
- Analog
- A/D (Y and composite) reference voltage low-level input
-
-
67 VREFMLY
68 VREFMY
69 VREFHMY
70 VREFHY
I
- Analog
I
- Analog
I
- Analog
I
- Analog
A/D (Y and composite) intermediate reference potential input
-
(Capacitance coupling to AVSS)
- ^{A/D (Y and composite) intermediate reference potential input}
(Capacitance coupling to AVSS)
A/D (Y and composite) intermediate reference potential input
-
(Capacitance coupling to AVSS)
- A/D (Y and composite) reference voltage high-level input
-
-
-
-
-
-
-
-
71 AVSS9
GND
-
-
- A/D (Y and composite) use
-
-
72 AVDD9
Power supply 3.3 V
-
- A/D (Y and composite) use
-
-
73 VSS
GND
-
-
- Digital use
-
-
74 ANACLK
O
3.3 V CMOS
2 mA 6.75-MHz output
-
-
75 VDD3
Power supply 3.3 V
-
- Digital I/O (3.3 V) use
-
-
76 GCP
O
3.3 V CMOS
2 mA Clamp pulse (sync chip) output
27 MHz -
77 TESTIO9
I/O 3.3 V CMOS-100 kΩ PD 4 mA Test I/O (MSB) (open or VSS)
-
-
78 TESTIO8
I/O 3.3 V CMOS-100 kΩ PD 4 mA Test I/O (open or VSS)
-
-
79 VSS
GND
-
-
- Digital use
-
-
80 TESTIO7
I/O 3.3 V CMOS-100 kΩ PD 4 mA Test I/O (open or VSS)
-
-
81 TESTIO6
I/O 3.3 V CMOS-100 kΩ PD 4 mA Test I/O (open or VSS)
-
-
82 VDDI
Power supply 1.8 V
-
- Internal digital use
-
-
83 TESTIO5
I/O 3.3 V CMOS-100 kΩ PD 4 mA Test I/O (open or VSS)
-
-
84 TESTIO4
I/O 3.3 V CMOS-100 kΩ PD 4 mA Test I/O (open or VSS)
-
-
85 VSS
GND
-
-
- Digital use
-
-
86 VDDDRAM0 Power supply 2.5 V
-
- DRAM (5 Mbits) use
-
-
87 VSSDRAM0
GND
-
-
- Digital use
-
-
88 TESTIO3
I/O 3.3 V CMOS-100 kΩ PD 4 mA Test I/O (open or VSS)
-
-
89 TESTIO2
I/O 3.3 V CMOS-100 kΩ PD 4 mA Test I/O (open or VSS)
-
-
90 VDD3
Power supply 3.3 V
-
- Digital I/O (3.3 V) use
-
-
91 TESTIO1
I/O 3.3 V CMOS-100 kΩ PD 4 mA Test I/O (open or VSS)
-
-
92 TESTIO0
I/O 3.3 V CMOS-100 kΩ PD 4 mA Test I/O (LSB) (open or VSS)
-
-
93 VSS
GND
-
-
- Digital use
-
-
94 TCK
I
3.3 V CMOS-100 kΩ PD - Boundary scan clock input
-
-
95 TDO
O
3.3 V 3-state CMOS 2 mA Boundary scan data output
-
-
96 VDDI
Power supply 1.8 V
-
- Internal digital use
-
-
97 TDI
I
3.3 V CMOS-100 kΩ PU - Boundary scan data input
-
-
98 TRST
I
3.3 V CMOS-100 kΩ PU - Boundary scan reset input (VSS or RST when not used）
-
-
99 TMS
I
3.3 V CMOS-100 kΩ PU - Boundary scan mode input
-
-
100 VSS
GND
-
-
- Digital use
-
-
101 TEST5
I
3.3 V CMOS-100 kΩ PD - Test mode (MSB) (open or VSS)
-
-
102 TEST4
I
3.3 V CMOS-100 kΩ PD - Test mode (open or VSS)
-
-
103 TEST3
104 TEST2
I
3.3 V CMOS-100 kΩ PD - Test mode (open or VSS)
I
3.3 V CMOS-100 kΩ PD - Test mode (open or VSS)
-
-
-
-
When the boundary scan function is not used, set the TRST pin (pin 98) to reset input or VSS. *2
SDF00032BEM
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