MN673794 Datasheet, PDF (13/42 Pages) Panasonic Semiconductor – LSI FOR MPEG

MN673794
[d] System Clock Async/Multiple Bus Interface
Figure 3.4 (d) is the timing chart of the interface.
CLK (I)
CS (I)
Write timing
WE (I)
Address (I)
/Data (I)
Read timing
RE (I)
Address (I)
/Data (O)
t cyc
Address Valid
tWAS
tWAH
Address Valid
tRAS
tRAH
Data Valid
tWDS
tWDH
tRREDT
Data Valid
tRCSDT
Parameter
Symbol Min Typ Max Unit
27-MHz clock cycle
tCYC
37
ns
Write address setup
ns
（based on falling edge of address latch enable ALE） ^{tWAS tCYC}
Write address hold
ns
（based on falling edge of address latch enable ALE） ^{tWAH tCYC}
Read address setup
ns
（based on falling edge of address latch enable ALE） ^tRAS
tCYC
Read address hold
ns
（based on falling edge of address latch enable ALE） ^{tRAH tCYC}
Write data setup
ns
（based on rising edge of write enable WE）
tWDS
tCYC
Write data hold
(based on rising edge of write enable WE)
tWDH
tCYC
ns
Read data delay
(based on falling edge of read enable RE)
tRREDT
0
tCYC
ns
Read data hold
(based on rising edge of chip select CS)
tRCSDT
0
ns
Figure 3.3 (d) Microcontroller Interface Timing 4
* Address, Data, CS, WE, and RE input signals are input, not synchronizing with the CLK clock signal.
SDF00032BEM
13