MN673794 Datasheet, PDF (10/42 Pages) Panasonic Semiconductor – LSI FOR MPEG

MN673794
(3) Timing
[a] System Clock Async/Separation Bus Interface
Figure 3.3 (a) is the timing chart of the interface.
MAD[6:0]
MDA[15:0]
MCSALE
MNRE
MNWENBW
READ cycle (trdc)
Valid
Read Data
trdout
trdw
WRITE cycle (twrc)
tawrs
tawrh
Valid
tdwrs
tdwrh
Write Data
twrcs w
twrw cs
twrw
Timing
[ns]
Min
Max
trdc
Read cycle
148
–
trdout
Read data valid
–
30
twrc
Write cycle
148
–
trdw
Read pulse (MNRE) width
74
–
twrw
Write pulse (MNWENBW) width
74
–
twrcs_w CS enable after WE active
10
–
twrw_cs WE negate after CS disable
10
–
tdwrs
Write data setup
twrw
–
tdwrh
tawrs
tawrh
Write data hold
0
–
Write address setup
twrw
–
Write address hold
10
–
Figure 3.3 (a) Microcontroller Interface Timing 1
* Note)
• When the signal timing changes to the read cycle from the write cycle, data reading must start at least 50
ns after the write cycle completes.
• In the case of continuous data writing, a minimum of 148 ns is required between the falling edge of the
present write enable (MNWENBW) and that of the next write enable.
SDF00032BEM
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