MN673794 Datasheet, PDF (17/42 Pages) Panasonic Semiconductor – LSI FOR MPEG

MN673794
2. Y/C separation
Register name Address
Description
HYOZI
F3DSEL
F2DSEL
0008h[6]
0008h[5:3]
0008h[2:0]
The detected movement area is displayed dark (for evaluation).
0: Normal 1: Movement detection display
A threshold value to determine movement with two-frame
differential movement detected. (Compared with the 9-bit absolute
value converted from the 10-bit difference between the 9-bit input
signal and 2-frame, 9-bit delay signal.)
000: 3D fixed 001: 4 or more 010: 8 or more 011: 12 or more
100: 16 or more 101: 20 or more 110: 24 or more 111: 28 or more
(To fix the setting to 3D, set the F3DSEL register to 000 and the F2DSEL
register to 000. To fix the setting to 2D, set the F3DSEL to any value
other than 000 and set the F2DSEL to 000.)
A threshold value to determine movement with one-frame
differential movement detected. (Compared with the 9-bit absolute
value converted from the 10-bit difference between the 9-bit input
signal and 1-frame, 9-bit delay signal.)
000: 3D fixed 001: 4 or more 010: 8 or more 011: 12 or more
100: 16 or more 101: 20 or more 110: 24 or more 111: 28 or more
(To fix the setting to 3D, set the F3DSEL register to 000 and the F2DSEL
register to 000. To fix the setting to 2D, set the F3DSEL to any value
other than 000 and set the F2DSEL to 000.)
Default
(Recommend-
ed value)
0
100
100
3. Y/C delay adjustment
Register name Address
cdly2
0009h[7:6]
cdly1
tbccdly
0009h[5]
0009h[9:8]
cflgdly
0029h[0]
Description
Used to adjust the delay of the component C signal (in 4fsc increments).
(DD conversion output of C signal of analog input processing block)
00: No delay 01: +1 clock
10: -2 clock 11: -1 clock
Used to adjust the delay of the component C signal (in 27 MHz increments).
(LPF output of C signal of analog input processing block)
00: No delay 01: +1 clock
Used to adjust the delay of the CbCr multiple signal (in 4fsc increments).
(Before TBC input into the analog input processing block)
00: No delay 01: +1 clock
10: -2 clock 11: -1 clock
Used to reverse the polarity of the CbCr separation flag for the CbCr
multiple signal. If the tint is reversed with tbccdly delay adjustments, invert
this flag. (Before TBC input into the analog input processing block)
0: No reversion 1: Reversion
Default
(Recommend-
ed value)
00
0
00
(11)
0
(1)
SDF00032BEM
17