MN673794 Datasheet, PDF (21/42 Pages) Panasonic Semiconductor – LSI FOR MPEG

MN673794
7. Frame sync
Register name Address
wr_offset
0017h[4:0]
Description
Frame sync, write line start position offset
(23 lines + offset value)
Default
(Recommend
-ed value)
00000
8. Analog power down (Possible to reduce the power consumption of the corresponding functions when the
functions are not in use.)
Register name Address
yadpdwn
0039h[8]
cadpdwn
0039h[7]
Test0dapdwn 0039h[6]
Test1dapdwn 0039h[5]
Test2dapdwn 0039h[4]
agcdapdwn 0039h[3]
accdapdwn 0039h[2]
clpdapdwn 0039h[1]
testpllpdwn 0039h[0]
Description
Used to power down the component Y/composite Y (analog input)
ADC.
0: Normal 1: Power down
Used to power down the component C (analog output) ADC.
0: Normal 1: Power down
Used to power down the DAC for test use.
0: Normal 1: Power down
Used to power down the DAC for test use.
0: Normal 1: Power down
Used to power down the DAC for test use.
0: Normal 1: Power down
Used to power down the AGC control DAC.
0: Normal 1: Power down
Used to power down the ACC control DAC.
0: Normal 1: Power down
Used to power down the clamp control DAC.
0: Normal 1: Power down
Used to power down the PLL for test use
0: Normal 1: Power down
Default
(Recommend
-ed value)
0
0
0
(1)
0
(1)
0
(1)
0
0
0
0
(1)
SDF00032BEM
21