MN673794 Datasheet, PDF (11/42 Pages) Panasonic Semiconductor – LSI FOR MPEG

MN673794
[b] System Clock Async/Multiple Bus Interface
Figure 3.3 (b) is the timing chart of the interface.
MAD[6:0]
MDA[15:0]
MCSALE
MNRE
MNWENBW
READ cycle (trdc)
Address
trdout
Read Data
Valid
trdw
WRITE cycle (twrc)
Address
twrs twrh
Write Data
twrw
Timing
[ns]
Min
Max
trdc Read cycle
148
–
trdout Read data valid
–
30
twrc Write cycle
148
–
trdw Read pulse (MNRE) width
74
–
twrw Write pulse (MNWENBW) width
74
–
twrs Write data setup
twrw
–
twrh Write data hold
10
–
Figure 3-3 (b) Microcontroller Interface Timing 2
SDF00032BEM
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