MN673794 Datasheet, PDF (12/42 Pages) Panasonic Semiconductor – LSI FOR MPEG

MN673794
[c] System Clock Sync/Separation Bus Interface
Figure 3.3 (c) is the timing chart of the interface.
CLK (I)
t cyc
Address (I)
Address Valid
CS (I)
Write timing
WE (I)
Data (I)
Read timing
RE (I)
Data (O)
t RREDT
Data Valid
tWDS
tWDH
Data Valid
t RCSDT
Parameter
Symbol Min Typ Max Unit
27-MHz clock cycle
tCYC
37
ns
Write data setup
（based on rising edge of write enable WE）
tWDS
tCYC
ns
Write data hold
(based on rising edge of write enable WE)
tWDH
tCYC
ns
Read data delay
(based on falling edge of read enable RE)
tRREDT
0
tCYC
ns
Read data hold
(based on rising edge of chip select CS)
tRCSDT
0
ns
Figure 3.3 (c) Microcontroller Interface Timing 3
• Address, Data, CS, WE, and RE input signals are input, not synchronizing with the CLK clock signal.
• The CS must be disabled (i.e., set to high) whenever data is read from or written to any address.
SDF00032BEM
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