TCC-106 Datasheet, PDF (9/24 Pages) ON Semiconductor – Six-Output PTIC Control IC

TCC−106
Boost Control
The TCC−106 integrates an asynchronous current control
boost converter. It operates in a discontinuous mode and
features spread−spectrum circuitry for Electro−Magnetic
Interference (EMI) reduction. The average boost clock is
2 MHz and the clock is spread between 0.8 MHz and 3.2 MHz.
Boost Output Voltage (VHV) Control Principle
The asynchronous control starts the boost converter as
soon as the VHV voltage drops below the reference set by
the 4−bit DAC and stops the boost converter when the VHV
voltage rises above the reference again.
Due to the slow response time of the control loop, the
VHV voltage may drop below the set voltage before the
control loop compensates for it. In the same manner, VHV
can rise higher than the set value. This effect may reduce the
maximum output voltage available. Please refer to Figure 6
below.
The asynchronous control reduces switching losses and
improves the output (VHV) regulation of the DC/DC
converter under light load, particularly in the situation
where the TCC−106 only maintains the output voltages to
fixed values.
CHV
Recharge
CHV
Discharge
VHV
Set VHV
Delay
Delay
Boost
Running
Figure 5. VHV Voltage Waveform
Delay
Time
High Impedance (High Z) Feature
In shutdown mode the OUT pins are set to a high
impedance mode (high Z). Following is the principle of
operation for the control IC:
1. The DAC output voltage V_OUT is defined by:
DAC code
V_OUT + ₂₅₅
24 V 2
(eq. 1)
2. The voltage VHV defines the maximum supply
voltage of the DAC supply output regulator and is
set by a 4−bit control.
3. The maximum DAC DC output voltage V_OUT is
limited to (VHV – 2 V).
4. The minimum output DAC voltage V_OUT is 1.0 V
max.
Figure 6. DAC Output Range Example A
Figure 7. DAC Output Range Example B
Digital Interface
The control IC is fully controlled through a digital
interface (DATA, CLK, CS). The digital interface auto−
matically detects and responds to MIPI RFFE interface
commands, 3−wire 30−bit serial interface commands or
3−wire 32−bit serial interface commands. Auto−detection is
accomplished on a frame by frame basis. The digital
interface is described in the following sections of this
document, for detailed programming instructions please
refer to the programming guide, available by contacting
ON Semiconductor.
3−Wire Serial Interface
The 3−wire serial interface operates in a synchronous
write−only 3−wire slave mode. 30−bit or 32−bit message
length is automatically detected for each frame. If CS
changes state before all bits are received then all data bits are
ignored. Data is transmitted most significant bit first and
DATA is latched on the rising edge of CLK. Commands are
latched on the falling edge of CS.
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