TCC-106 Datasheet, PDF (12/24 Pages) ON Semiconductor – Six-Output PTIC Control IC

TCC−106
Table 13. 3−WIRE SERIAL INTERFACE ADDRESS MAP
1
0
0
1
0
Reserved
to
Reserved
1
1
1
1
1
Turbo−Charge Mode
The TCC−106 control IC has a Turbo−Charge mode that
significantly shortens the system settling time when
changing programming voltages. In Turbo−Charge mode
the DAC output target voltage is temporarily set to either a
delta voltage above or a delta voltage below the actual
desired target for the TCDLY time. It is recommended that
V_HV be set to 24 V when using Turbo−Charge mode.
During glide mode the output voltage of a DAC is either
increased or decreased to its set end point, in max 255 steps,
where each DAC time step can be programmed between
2 ms to 64 ms. For programming the glide mode refer to the
application note (coming soon). A programming input is not
required to maintain a glide transition, all step controls are
maintained by the part. Only the inputs to define the glide
need to be programmed.
Glide Mode
Unlike turbo mode, which is intended to reduce the
charging time, the glide mode extends the transition time of
each DAC output. Each DAC has an individual control for
turbo mode, glide mode or regular voltage switching. The
glide mode can be enabled for a particular DAC through the
INDEX register, by setting DAC State to ‘1’ when glide
mode is enabled, turbo mode is off for a particular DAC, but
one DAC can be gliding while the other is turbo.
RF Front−End Control Interface (MIPI RFFE Interface)
The TCC−106 is a read/write slave device which is fully
compliant to the MIPI Alliance Specification for RF
Front−End Control Interface (RFFE) Version 1.10.00 26
July 2011. This device is rated at full−speed operation for
1.65 V<VIO<1.95 V and at half−speed operation for
1.1 V<VIO<1.65 V. When using the MIPI RFFE interface
the CS pin must be grounded externally.
CLK
TD_SETUP
TD_HOLD
TD_SETUP
TD_HOLD
DATA
Figure 9. MIPI−RFFE Signal Timing during Master Writes to PTIC Control IC
CLK
T_{READ_ACCESS}
T_SDATAOTR
T_{READ_ACCESS}
T_SDATAOTR
CLK
T_SDATAZ
DATA
Figure 10. MIPI−RFFE Signal Timing during Master
Reads from PTIC Control IC
DATA
Bus Park Cycle
Figure 11. Bus Park Cycle Timing
when MIPI−RFFE Master Reads
from PTIC Control IC
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