TCC-106 Datasheet, PDF (14/24 Pages) ON Semiconductor – Six-Output PTIC Control IC

TCC−106
The control IC contains twenty−four 8−bit registers. Register content is described in Table 15. Some additional registers
implemented as provision, are not described in this document.
Table 15. MIPI RFFE ADDRESS MAP
Register
Address
Description
0x00
DAC Configuration (Enable Mask)
Purpose
High voltage output enable mask
Access
Type
Write
Size (bits)
7
0x01
Turbo Register DAC A, B & C
Turbo−charge configuration DAC A, B & C
Write
8
0x02
DAC A Register
OUT A value [6:0], Turbo Index [7]**
Write
8
0x03
DAC B Register
OUT B value [6:0], Turbo Index [7]**
Write
8
0x04
DAC C Register
OUT C value [6:0], Turbo Index [7]**
Write
8
0x05
Turbo Register DAC D, E & F
Turbo−charge configuration DAC D,E & F
Write
8
0x06
DAC D Register
OUT D value [6:0], Turbo Index [7]**
Write
8
0x07
DAC E Register
OUT E value [6:0], Turbo Index [7]**
Write
8
0x08
DAC F Register
OUT F value [6:0], Turbo Index [7]**
Write
8
0x10
DAC Boost (VHV)
Settings for the boost high voltage
Write
8
0x11
Trigger register
Trigger configuration
Write
8
0x12
Turbo−Charge Delay DAC A, B, C
Turbo−charge delay steps
DAC A, B, C
Write
8
0x13
Turbo−Charge Delay DAC A, B, C
Turbo−charge delay, multiplication
DAC A, B, C
Write
8
0X14
Turbo−Charge Delay DAC D, E, F
Turbo−charge delay steps
DAC D, E, F
Write
8
0X15
Turbo−Charge Delay DAC D, E, F
Turbo−charge delay multiplication
DAC D, E, F
Write
8
0x1C
0x1D
0x1E
0x1F
Power Mode and Trigger Register
Product ID Register
Manufacturer ID Register
Unique Slave Identifier Register (USID)
Power mode & trigger control
PWR_MODE [7:6]
TRIG_REG [5:0]
Product number *
Hard coded into ASIC
MN (10 bits long)
Manufacturer ID[7:0]
Hard Coded into ASIC
Spare [7:6]
[5,4] = Manufacturer ID [9:8]
USID [3:0]
Write
8
Write
8
Write
8
Write
8
*The second least significant bit can be programmed in OTP during manufacture
** The details for configuration of Turbo mode should be ascertained from the Programming Guide, available from ON Semiconductor
Configuration Settings
Table 16. DAC CONFIGURATION (ENABLE MASK) at [0x00] Defaults shown as (x)
Bit 6 (1)
Bit 5 (0)
Bit 4 (0)
Bit 3 (0)
Bit 2 (0)
SSE
DAC E
DAC F
DAC A
DAC B
Bit 1 (0)
DAC C
Bit 0 (0)
DAC D
SSE = 0 spread spectrum disabled, SSE = 1 spread spectrum enabled (default), this controls the average boost clock which
is nominally 2 MHz and spread between 0.8 MHz and 3.2 MHz when enabled (default). The hardware does not limit driving
more than three DACs at the same time, however it is recommended to have max three DACs changing outputs at one time,
no restrictions exist as to which three.
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