TCC-106 Datasheet, PDF (16/24 Pages) ON Semiconductor – Six-Output PTIC Control IC

TCC−106
MIPI RFFE TRIG Operation
The MIPI RFFE Trigger mode can be used as a
synchronization signal to ensure that new DAC settings are
applied to the outputs at appropriate times in the overall
transceiver system. When the MIPI RFFE TRIG function is
enabled via [0x11] bit 4 the requested DAC voltage levels
are set up in the shadow registers and not transferred to the
destination registers until the trigger condition is met. In this
manner the change in output voltage levels are synchronized
with the MIPI RFFE TRIG command. If multiple DAC
voltage level requests are received before the TRIG event
occurs, only the last fully received DAC output voltage level
will be applied to the outputs.
The trigger configuration also provides for an additional
external TRIG pin to be used as a synchronization signal.
The external TRIG is independent from the built−in triggers
available within the MIPI RFFE interface. When the TRIG
input pin is enabled via [0x11] bit 4 the requested DAC
voltage levels are set up in the shadow registers and are not
transferred to the destination registers until the external
trigger condition is met. In this manner the change in output
voltage levels are synchronized with the external TRIG
event. The external TRIG input is referenced to VIO. To
improve interfacing options the polarity of external TRIG is
programmable via [0x11] bit 1.
If the external trigger function is not needed in the
application, the TRIG pin should be grounded and the TRIG
function disabled. When TRIG pin is disabled by register
[0x11] ‘TRIG Select’ = ‘1’ (default) and register [0x10]
‘Trigger Mask 0, 1, 2’ = ‘1’:
• The requested DAC voltage levels for DAC A, B, C are
applied to the outputs all together at the same time,
after DAC C value is written. This event will not affect
the outputs of DAC D, E, F.
• The requested DAC voltage levels for DAC D, E, F are
applied to the outputs all together at the same time,
after DAC F value is written. This event will not affect
the outputs of DAC A, B, C.
• Optionally a configuration register can select the last
DAC to be written in order to trigger internally the
update of all six DACs at the same time. For example
the configuration register can select that a write to DAC
B value will trigger internally the update of all six
DACs outputs.
Table 20. TRIGGER CONFIGURATION at [0x11]
Bit 7 Bit 6 Bit 5
Bit 4
Res*
0
Res*
0
Res*
0
TRIG Select
0 = Ext TRIG Pin
1 = RFFE Trigger
*Reserved bits
Bit 3
Bit 2
Reserved
0
Bit 1
TRIG Edge
0 = Active Falling
1 = Active Rising
Bit 0
Mask Ext TRIG
1 = Mask Trig Pin
Table 21. EXTERNAL TRIGGER CONFIGURATION BIT SETTING AT [0x11]
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Description
0
−
−
X
0
External trigger pin is enabled. Sending the RFFE message will load a ‘shadow’
register only. Only upon an active signal on external TRIG pin are the output re-
gisters loaded with the new voltage settings which are then applied to the outputs.
1
−
−
X
X
The MIPI RFFE trigger is enabled (Default)
0
−
−
0
0
External TRIG pin signal is active falling
0
−
−
1
0
External TRIG pin signal is active rising (Default)
X
−
−
X
0
External trigger pin is not masked
X
−
−
X
1
Mask external trigger pin (Default)
Table 22. POWER MODE AND TRIGGER REGISTER [0x1C]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PM1
PM0
Trigger Mask 2 Trigger Mask 1 Trigger Mask 0
Bit 2
Trigger 2
Bit 1
Trigger 1
Bit 0
Trigger 0
Writing a logic one (‘1’) to the bits 0, 1 or 2 (Trigger 0, 1
or 2) moves data from the shadow registers into the
destination registers. Default for bit 0, 1 and 2 is logic low.
If trigger mask bit 0, 1 or 2 is set (‘1’) the trigger 0, 1 or
2 are disabled respectively and the data goes directly to the
destination register. Default for bit 3, 4 and 5 is logic low.
All three triggers behave in the same way as the external
pin TRIG. When each of these triggers is set using the MIPI
RFFE interface the results are the same as when an active
edge is applied to the TRIG pin when external pin TRIG is
selected
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