TCC-106 Datasheet, PDF (11/24 Pages) ON Semiconductor – Six-Output PTIC Control IC

TCC−106
Figure 8. 3−wire Serial Interface Signal Timing
SPI Frame Length Decoding
30−bit or 32−bit frame length is automatically detected.
The length of the frame is defined by the number of clock
rising edges while CS is kept high. The TCC−106 will not
respond to a SPI command if the length of the frame is not
exactly 30 bits or 32 bits. SPI registers are write only.
SPI Frame Structure
Table 11. 32 BITS FRAME: ADDRESS DECODING (1, 2, 3, 4, 5 or 6 OUTPUTS)
H0
H1
R/W A12 A11 A10 A9 A8 A7 A6 A5
1
1
0
1
0
1
0
0
1
0
0
ON Semiconductor Header R/W
Device ID
Specific Device ID
A4 A3 A2 A1 A0
X
X
X
X
X
Register Address for Operation
Table 12. 30 BITS FRAME: ADDRESS DECODING (1, 2, 3, 4, 5 or 6 OUTPUTS)
R/W
A12
A11
A10 A9
A8
A7
A6
A5 A4
A3
A2
A1
A0
0
1
0
1
0
0
1
0
0
X
X
X
X
X
R/W
Device ID
Specific Device ID
Register Address for Operation
Table 13. 3−WIRE SERIAL INTERFACE ADDRESS MAP
A4 A3 A2 A1 A0
Data[15:8]
Data[7:0]
0
0
0
0
0
Turbo−Charge Settings for DAC A, B, C
DAC C
0
0
0
0
1
DAC B
DAC A
0
0
0
1
0
Turbo−Charge Settings for DAC D, E, F
DAC F
0
0
0
1
1
DAC E
DAC D
0
0
1
0
0 Turbo−Charge Delay Parameters for DAC A, B, C Turbo Threshold Delay Settings for A, B, C
0
0
1
0
1 Turbo−Charge Delay Parameters for DAC D, E, F Turbo Threshold Delay Settings for A, B, C
1
0
0
0
0
Mode Select + Control IC Setup
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