TCC-106 Datasheet, PDF (10/24 Pages) ON Semiconductor – Six-Output PTIC Control IC

TCC−106
Table 10. 3−WIRE SERIAL INTERFACE SPECIFICATION
(T_A = −30 to +85°C; 2.3 V<AVDD<5.5 V; 1.1 V<VIO<3.0 V; unless otherwise specified)
Parameter
Description
Min
Typ
Max
F_CLK
T_CLK
Clock Frequency
Clock Period
−
−
26
38.4
−
−
N_BIT
Bits Number
−
30/32
−
T_HIGH
T_LOW
TCS_SETUP
Clock High Time
Clock Low Time
CS Set−up Time
13
−
−
13
−
−
5
−
−
TCS_HOLD
CS Hold Time
5
−
−
TD_SETUP
Data Set−up Time
4
−
−
TD_HOLD
Data Hold Time
4
−
−
T_SUCC
CS Low Time Between
Successive Writes
38.4
−
−
T_SUCC
CS Low Time Between
1,500
−
−
Successive DAC Update Writes
C_CLK
Input Capacitance
−
−
5
C_DATA
Input Capacitance
−
−
8.3
C_CS
Input Capacitance
−
−
5
C_TRIG
Input Capacitance
−
−
10
V_IH
Input Logic Level High
0.7 x VIO
−
VIO + 0.3
V_IL
Input Logic Level Low
−0.3
−
0.3 x VIO
I_{IH_DATA}
Input Current High
−2
−
10
I_{IL_DATA}
Input Current Low
−2
−
1
I_{IH_CLK,CS}
Input Current High
−1
−
10
I_{IL_CLK,CS}
Input Current Low
−1
−
1
V_{TP_TRIG}
Positive Going Threshold Volt-
0.4 x VIO
−
0.7 x VIO
age
V_{TN_TRIG}
Negative Going Threshold Volt- 0.3 x VIO
−
0.6 x VIO
age
V_{H_TRIG}
Hysteresis Voltage (V_TP – V_TN) 0.1 x VIO
−
0.4 x VIO
I_{IH_TRIG}
TRIG Input Current High
−2
−
10
I_{IL_TRIG}
TRIG Input Current Low
−2
−
1
Unit
MHz
ns
bits
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF
pF
V
V
mA
mA
mA
mA
V
Comments
Auto−detection 30−bit or
32−bit
70% rising edge of CS to
30% rising edge of first
clock cycle
30% falling edge of last
clock cycle to 70% falling
edge of CS
Relative to 30% of CLK
rising edge
relative to 70% of CLK ris-
ing edge
70% falling edge of CS to
70% rising edge of CS
Time between groups of
DAC update reg [00000] &
[00001] writes
CLK pin
DATA pin
CS pin
TRIG pin
DATA, CLK, CS
DATA, CLK, CS
DATA
DATA
CLK, CS
CLK, CS
TRIG
V
TRIG
V
TRIG
mA
TRIG=0.8 x VIO
mA
TRIG=0.2 x VIO
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