AMIS-49587_15 Datasheet, PDF (32/56 Pages) ON Semiconductor – Power Line Carrier Modem

AMIS−49587
After this delay, the frame reception is finished. If the
length and the checksum are both correct, the local frame is
taken in account otherwise all previous characters are
discarded. The time out Inter Character (t_IC) is set by default
at 10 ms after a reset. The time out Inter character (t_IC) is
modified by the bit 7 of repeater parameter in the
configuration frame:
♦ bit 7 = 1 −> the t_IC value is constant at 10 ms,
♦ bit 7 = 0 −> the t_IC value represents 5 characters
depending on the communication speed (defined by
two local input ports BR0 and BR1).
See Table 29: Timings for Time−out Values.
Table 29. TIME-OUT VALUES
Time-out
Tpoll
Meaning
Delay max. awaited by the base micro between the T_REQ pull down
and the status message transmission (delay polling)
Value
20 ms
Tsr
Delay max. awaited by the AMIS−49587 between the end of the status
transmitting and the reception of the STX character in the base micro
frame (delay status/reception)
200 ms
Tack
Delay max. awaited by either the AMIS−49587 or the base micro
between the end of a transmitting and the reception of the ACK or NAK
character sent by the other (delay ACK).
40 ms
Twbc
Delay max. awaited by either the AMIS−49587 or the base micro
between the end of a reception and the transmission of the next frame
(delay waiting before continue).
5 ms
Tic
Delay max. awaited by either the AMIS 49587 or the
base micro between two characters
Bit 7 = 1
10 ms
(delay inter characters)
Programmable with bit 7 of the repeater parameter in the ^{Bit 7 = 0}
4800 baud
10 ms
configuration frame
9600 baud
5 ms
6.4.8 Watchdog
The watchdog supervises the ARM and in case the
firmware doesn’t acknowledge at periodic times, a hard
reset is generated.
6.4.9 Configuration Registers
A number of configuration registers can be accessed by
the user by sending a WriteConfig_Request over the SCI
19200 baud
2.5 ms
38400 baud
1.25 ms
interface. See also paragraph Configuration of the
AMIS−49587. An overview of the accessible configuration
registers is given below:
R_CONFIG register configures the AMIS_49587 in the
correct mode. The R_CONFIG register is controlled by the
embedded software and can be accessed via a
WriteConfig_Request.
Table 30. R_CONF[9:0] (See Table 41: Configuration Parameters)
ARM Register
Hard Reset Soft Reset
Description
R_CONF[7]
0
−
TX_DATA_PRE_SLOT_SEL
R_CONF[5:3]
000
−
MODE
R_CONF[2:1]
00
−
BAUDRATE
R_CONF[0]
0
−
MAINS_FREQ
Where:
TX_DATA_PRE_SLOT_SEL: 0:
1:
MODE:
000:
001:
010:
011:
1xx:
BAUDRATE:
00:
01:
10:
TX_DATA/PRE_SLOT is PRE_SLOT output pin
TX_DATA/PRE_SLOT is TX_DATA output pin
Initialization
Master Mode
Slave Mode
Reserved
Test Mode
6 data bits per mains period = 300 baud @ 50 Hz
12 data bits per mains period = 600 baud @ 50 Hz
24 data bits per mains period = 1200 baud @ 50 Hz
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