AMIS-49587_15 Datasheet, PDF (10/56 Pages) ON Semiconductor – Power Line Carrier Modem

AMIS−49587
CRC
CRC is a 5V compliant open drain output. An external pull−up resistor defines the logic high level as illustrated in Figure 5.
A typical value for this pull−up resistance “R” is 10 kW. The signal on this output depends on the cyclic redundancy code result
of the received frame. If the cyclic redundancy code is correct CRC = 1 during the pause between 2 time slots.
RESB
RESB is a digital input pin. It is used to perform a hardware reset of the AMIS−49587. This pin supports a 5 V voltage level.
The reset is active when the signal is low (0 V).
TEST
TEST is a digital input pin. It is used to enable the test mode of the chip. Normal mode is activated when TEST signal is low
(0 V). For normal operation, the TEST pin may be left unconnected. Due to the internal pulldown, the signal is maintained to
low (0 V). TEST pin is not 5 V safe.
TX_ENB
TX_ENB is a digital output pin. It is low when the transmitter is activated. The signal is available to turn on the line driver.
TX_ENB is a 5 V safe with open drain output, hence a pull−up resistance is necessary achieve the requested voltage level
associated with a logical one. See also Figure 5 for reference.
TX_OUT
TX_OUT is the analog output pin of the transmitter. The provided signal is the S−FSK modulated frames. A filtering operation
must be performed to reduce the second order harmonic distortion. For this purpose an active filter is realized. Figure 7 gives
the representation of this filter.
FROM LINE
DRIVER
TO TX POWER
OUTPUT STAGE
R3
C3
C4
ALC _IN
R₂
R₁
C1 _{TX_OUT}
C₂
VSSA
TX_EN
Transmitter (S−FSK Modulator)
ALC
control
LP
Filter
ARM
Interface
&
Control
Figure 7. TX_OUT Filter
ALC_IN
ALC_IN is the automatic level control analog input pin. The signal is used to adjust the level of the transmitted signal. The
signal level adaptation is based on the AC component. The DC level on the ALC_IN pin is fixed internally to 1.65 V. Comparing
the peak voltage of the AC signal with two internal thresholds does the adaptation of the gain. Low threshold is fixed to 0.4 V.
A value under this threshold will result in an increase of the gain. The high threshold is fixed to 0.6 V. A value over this threshold
will result in a decrease of the gain. A serial capacitance is used to block the DC components. The level adaptation is performed
during the transmission of the first two bits of a new frame. Eight successive adaptations are performed.
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