AMIS-49587_15 Datasheet, PDF (22/56 Pages) ON Semiconductor – Power Line Carrier Modem

AMIS−49587
6.1.4 Clock Generator and Timer
The CHIP_CLK and f_CLK are used to generate a number
of timing signals used for the synchronization and interrupt
generation. The timing generation has a fixed repetition rate
which corresponds to the length of a physical subframe. (see
paragraph Send and Receive network data).
Start of the physical subframe
The timing generator is the same for transmit and receive
mode. When AMIS−49587 switches from receive to
transmit and back from transmit to receive, the
R_CHIP_CNT counter value is maintained. As a result all
timing signals for receive and transmit have the same
relative timing. The following timing signals are defined as:
R_CHIP_CNT ^{2871 2872 2879 0 1 2 3 4 5 6 7 8 9}
CHIP_CLK
63 64 65
BIT_CLK
BYTE_CLK
FRAME_CLK
PRE_BYTE_CLK
PRE_FRAME_CLK
PRE_SLOT
Figure 16. Timing Signals
CHIP_CLK is the output of the PLL and 8 times the bit rate on the physical interface. See also paragraph 50/60 Hz PLL
BIT_CLK is active at counter values 0,8,16, .. 2872 and inactive at all other counter values. This signal is used to indicate the
transmission of a new bit.
BYTE_CLK is active at counter values 0,64,128, .. 2816 and inactive at all other counter values. This signal is used to indicate
the transmission of a new byte.
FRAME_CLK is active at counter values 0 and inactive at all other counter values. This signal is used to indicate the
transmission or reception of a new frame.
PRE_BYTE_CLK is a signal which is 8 CHIP_CLK sooner than BYTE_CLK. This signal is used as an interrupt for the
internal microcontroller and indicates that a new byte for transmission must be generated.
PRE_FRAME_CLK is a signal which is 8 CHIP_CLK sooner than FRAME_CLK. This signal is used as an interrupt for the
internal microcontroller and indicates that a new frame will start at the next FRAME_CLK.
PRE_SLOT is logic 1 between the rising edge of PRE_FRAME_CLK and the rising edge of FRAME_CLK. This signal can
be provided at the digital output pin TX_DATA_PRE_SLOT when R_CONF[7] = 0 (See paragraph WriteConfigRequest, field
TX_DATA_PRE−SLOT_SEL) and can be used by the external host controller to synchronize its software with the
FRAME_CLK of AMIS−49587.
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