AMIS-49587_15 Datasheet, PDF (21/56 Pages) ON Semiconductor – Power Line Carrier Modem

V _MAINS
AMIS−49587
VIR _M50HZIN
ZeroCross
t
6 bit @ 300 baud
CHIP _CLK
tZCD
PLL in lock
Start of Physical PreFrame*
10 ms
*The start of the Physical Subframe is shifted back with R_ZC_ADJUST[7:0] x 26 mS = t_ZCD to compensate for the zero cross delay
Figure 14. Zero Cross Adjustment to Compensate for Zero Cross Delay (Example for 50 Hz)
The phase difference between the zero crossing of the
mains and CHIP_CLK can be tuned. This opens the
possibility to compensate for external delay t_ZCD(e.g. opto
coupler) and for the 1.9 V positive threshold VIR_M50HZIN of
the zero crossing detector. This is done by pre−loading the
PLL counter with a number value stored in register
R_ZC_ADJUST[7:0]. The adjustment period or granularity
is 26 ms. The maximum adjustment is 255 x 26 ms = 6.6 ms
which corresponds with 1/3rd of the mains sine period.
Table 23. ZERO CROSS DELAY COMPENSATION
R_ZC_ADJUST[7:0]
Compensation
0000 0000
0 ms
0000 0001
26 ms
0000 0010
52 ms
0000 0011
78 ms
…
…
1111 1101
6589 ms
1111 1110
6615 ms
1111 1111
6641 ms
6.1.3 Oscillator
The oscillator works with a standard parallel resonance
crystal of 24 MHz. XIN is the input to the oscillator inverter
gain stage and XOUT is the output.
XTAL _IN
XTAL _ OUT
R_X
24 MHz
CX
CX
V_SSA
Figure 15. Placement of the Capacitors and Crystal
with Clock Signal Generated Internally
For correct functionality the external circuit illustrated in
Figure 15 must be connected to the oscillator pins. For a
crystal requiring a parallel capacitance of 20 pF C_X must be
around 30 pF. (Values of capacitors are indicative only and
are given by the crystal manufacturer). To guarantee startup
the series loss resistance of the crystal must be smaller than
80 W. A parallel resistor R_X = 1 MW is recommended to
improve the clock symmetry.
The oscillator output f_CLK = 24 MHz is the base frequency
for the complete IC. The clock frequency for the ARM f_ARM
= f_CLK. The clock for the transmitter, f_{TX_CLK} is equal to
f_CLK / 2 or 12 MHz. All the transmitter internal clock signals
will be derived from f_{TX_CLK}. The clock for the receiver,
f_{RX_CLK} is equal to f_CLK / 4 or 6 MHz. All the receiver
internal clock signals will be derived from f_{RX_CLK}.
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