AMIS-49587_15 Datasheet, PDF (25/56 Pages) ON Semiconductor – Power Line Carrier Modem

AMIS−49587
output level is fixed to the programmed level in the register
R_ALC_CTRL[2:0]. See also paragraph.
WriteConfigRequest.
Table 25. FIXED TRANSMITTER OUTPUT
ATTENUATION
ALC_CTRL[2:0]
Attenuation
000
0 dB
001
−3 dB
010
−6 dB
011
−9 dB
100
−12 dB
101
−15 dB
110
−18 dB
111
−21 dB
Remark: The analog part of AMIS−49587 works with an
analogue ground REF_OUT. When connecting
AMIS−49587 to external circuitry working with another
ground one must make sure to place a decoupling capacitor.
6.3 RECEIVER PATH DESCRIPTION
6.3.1 Receiver Block Diagram
The receiver takes in the analog signal from the line
coupler, conditions it and demodulates it in a data−stream to
the communication controller. The operation mode and the
baud rate are made according to the setting in R_CONF,
R_FS and R_FM. The receive signal is applied first to a high
pass filter. Therefore AMIS−49587 has a low noise
operational amplifier at the input stage which can be used to
make a high pass active filter to attenuate the mains
frequency. This high pass filter output is followed by a gain
stage which is used in an automatic gain control loop. This
block also performs a single ended input to differential
output conversion. This gain stage is followed by a
continuous time low pass filter to limit the bandwidth. A 4^th
order sigma delta converter converts the analog signal to
digital samples. A quadrature demodulation for f_S and f_M is
than performed by the ARM micro, as well the handling of
the bits and the frames.
RX_OUT
RX_IN
LOW NOISE
OPAMP
Receiver (Analog Path)
FROM
DIGITAL
Gain
LPF
4th
Order
SD AD
TO
DIGITAL
REF_OUT
REF
1.65 V
Figure 19. Analog Path of the Receiver
FROM
ANALOG
Noise
Shaper
Receiver (Digital Path)
1^st
Decimator
Compen−
sator
TO
GAIN
AGC
Control
Abs
value
accu
FROM TRANSMITTER
fMI ^fMQ ^fSI ^f SQ
Quadrature Demodulator
2^nd
IM
Sliding
Decimator
Filter
fM
f MQ
2^nd
QM
Sliding
Decimator
Filter
fSI
2^nd
IS
Sliding
Decimator
fSQ
Filter
fS
2^nd
QS
Decimator
Sliding
Filter
SOFTWARE
Figure 20. Digital Path of the Receiver ADC and Quadrature Demodulation
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