AMIS-49587_15 Datasheet, PDF (19/56 Pages) ON Semiconductor – Power Line Carrier Modem

AMIS−49587
6 DETAILED HARDWARE DESCRIPTION
6.1 CLOCK AND CONTROL
According to the IEC 61334−5−1 standard, the frame data
is transmitted at the zero crossing of the mains voltage. In
order to recover the information at the zero crossing, a zero
crossing detection of the mains is performed. A
phase−locked loop (PLL) structure is used in order to allow
a more reliable reconstruction of the synchronization. The
output of this block is the clock signal CHIP_CLK, 8 times
over sampled with the bit rate. The oscillator makes use of
a precise 24 MHz quartz. This clock signal together with
CHIP_CLK is fed into the Clock Generator and time block.
Here several internal clock signals and timings are obtained
by the use of a programmed division scheme.
Clock and Control
M50Hz_IN
Zero
crossing
PLL
CHIP_CLK _{Clock Generator}
& Timer
OSC
Figure 11. Clock and Control Block
XIN XOUT
6.1.1 Zero Crossing Detector
M50HZ_IN is the mains frequency analog input pin. The
signal is used to detect the zero crossing of the 50 or 60 Hz
sine wave. This information is used, after filtering with the
internal PLL, to synchronize frames with the mains
frequency. In case of direct connection to the mains it is
advised to use a series resistor of 1 MW in combination with
two external clamp diodes in order to limit the current
flowing through the internal protection diodes.
3V 3_A
FROM
MAINS
1 MW
M50Hz_IN
Clock & Control
Debounce ^ZeroCross
Filter
PLL
CHIP_ CLK
Figure 12. Zero Cross Detector with Falling Edge Debouncer
The zero crossing detector output is logic zero when the
input is lower than the falling threshold level and a logic one
when the input is higher than the rising threshold level. The
falling edges of the output of the zero crossing detector are
de−bounced by a period between 0.5 ms and 1 ms. The
Rising edges are not de−bounced.
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