AMIS-49587_15 Datasheet, PDF (20/56 Pages) ON Semiconductor – Power Line Carrier Modem

V_MAINS
AMIS−49587
VIR_M50HZIN
VIF_M50HZIN
t
ZeroCross
tZCD
10 ms
tDEBOUNCE = 0,5 .. 1 ms
Figure 13. Zero Cross Detector Signals and Timing (Example for 50 Hz)
6.1.2 50/60 Hz PLL
The output of the zero crossing detector is used as an input
for a PLL. The PLL generates the clock CHIP_CLK which
is 8 times the bit rate and which is in phase with the rising
edge crossings. The PLL locks on the zero crossing from
negative to positive phase. The bit rate is always an even
multiple of the mains frequency, so following combinations
are possible:
In case no zero crossings are detected the PLL freezes its
internal timers in order to maintain the CHIP_CLK timing.
Table 22. CHIP_CLK IN FUNCTION OF SELECTED
BAUD RATE AND MAINS FREQUENCY
BAUD[1:0] MAINS_FREQ Baudrate CHIP_CLK
00
300
2400 Hz
01
600
4800 Hz
50 Hz
10
1200
9600Hz
11
2400
19200 Hz
00
360
2880 Hz
01
720
5760 Hz
60 Hz
10
1440
11520Hz
11
2880
23040 Hz
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