AMIS-49587_15 Datasheet, PDF (17/56 Pages) ON Semiconductor – Power Line Carrier Modem

AMIS−49587
the frame is correct, it is passed to the external
processor.
♦ Test Mode:
The Test Mode is used to test the compliance of a
PLC modem conforms to CENELEC. EN 50065−1
by a Continuous broadcast of f_S or f_M.
5.1.1. CONVERTING AMIS−49587−BASED DESIGNS
TO NCN49597
The NCN49597 is designed to allow easy adaptation of
printed circuit board designs using the AMIS−49587. All
connected pins of the latter (QFN package) are present in the
same location in the NCN49597.
Four important hardware changes must be noted.
Most of the not−connected (NC) pins of the AMIS−49587
are functional in the NCN49597. If these pins were
previously connected to ground (a commendable practice)
this must be taken into account. IO4–IO10 are usually
configured as inputs and can therefore be grounded safely.
However, it must be considered that some NC pins of
AMIS−49587 are outputs in the NCN49597. These include
SDO, SCK and, CSB. IO0 and IO1 are used typically used
by the firmware as status indicators. IO3 is used by the ON
PL110 firmware for controlling the amplifier enable signal.
Secondly, the NCN49597 incorporates an internal 1.8 V
regulator to power the digital core. For stability, a 1 mF
capacitor to ground must be connected on pin 19
(VDD1V8).
In addition, the lowest baud rate setting of the
AMIS−49587 serial interface (BR0 & BR1 pulled low; 4800
baud) has been replaced by 115200 baud. All other BR0 and
BR1 settings will result in the same baud rate.
Finally, a 48 MHz crystal is required for the NCN49597;
the AMIS−49587 used a 24 MHz crystal.
The firmware running on the modem has been updated
substantially compared to the AMIS−49587. As a result, the
interface protocol between the user microcontroller and the
modem is completely different. Refer to the firmware
datasheet for details.
5.2 FUNCTIONAL DESCRIPTION
The block diagram below represents the main functional
units of the AMIS−49587:
TO Power Amplifier
TX _ ENB
TX_OUT
ALC _ IN
Transmitter (S−FSK Modulator)
LP
Filter
D/A
FROM Line Coupler
RX _OUT
RX _IN
Receiver (S− FSK Demodulator)
AAF
AGC
A/D
REF _ OUT
REF
Transmit Data
& Sine Synthesizer
S−FSK
Demodulator
M50 Hz_ IN
Clock and Control
Zero
crossing
PLL
Clock Generator
& Timer
OSC
AMIS−49587
Communication Controller
ARM
Risc
Core
Serial
Comm.
Interface
Local Port
Test
5
Control
POR
Watchdog
Timer 1 & 2
TxD
RxD
T_ REQ
BR 0
BR 1
TO Application
Micro Controller
RX _DATA
CRC
TX_DATA / PRE _SLOT
JTAG I /F
TEST
RESB
Data
RAM
Program
ROM
Interrupt
Control
VDDA VSSA VDDD VSSD
XIN XOUT
Figure 9. S−FSK Modem AMIS−49587 Block Diagram
PC20091019.2
5.2.1 Transmitter
The AMIS−49587 Transmitter function block prepares
the communication signal which will be sent on the
transmitting channel during the transmitting phase. This
block is connected to a power amplifier which injects the
output signal on the mains through a line−coupler.
5.2.2 Receiver
The analog signal coming from the line−coupler is low
pass filtered in order to avoid aliasing during the conversion.
Then the level of the signal is automatically adapted by an
automatic gain control (AGC) block. This operation
maximizes the dynamic range of the incoming signal. The
signal is then converted to its digital representation using
sigma delta modulation. From then on, the processing of the
data is done in a digital way. By using dedicated hardware,
a direct quadrature demodulation is performed. The signal
demodulated in the base band is then low pass filtered to
reduce the noise and reject the image spectrum.
Clock and Control
According to the IEC−61334−5−1 standard, the frame
data is transmitted at the zero crossing of the mains voltage.
In order to recover the information at the zero crossing, a
zero crossing detection of the mains is performed. A
phase−locked loop (PLL) structure is used in order to allow
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