AMIS-30522 Datasheet, PDF (24/29 Pages) AMI SEMICONDUCTOR – Micro-stepping Motor Driver

AMIS-30522
Table 27: SPI Control Parameter Overview EMC[1:0]
Index
EMC[1:0]
Slope (V/μs)
0
0
0
150
1
0
1
100
2
1
0
50
3
1
1
25
SM[2:0]
Selects the micro-stepping mode.
Table 28: SPI Control Parameter Overview SM[2:0]
Index
0
1
2
SM[2:0]
000
001
010
Step Mode
1_/32
1_/16
1_/8
3
011
¼
4
100
½
5
101
½
6
110
Full
7
111
N/A
Remark
Turn-on and turn-off voltage slope 10% to 90%
“
“
“
Remark
Micro-step
Micro-step
Micro-step
Micro-step
Uncompensated half-step
Compensated half-step
Full step
For future use
9.4 SPI Status Register Description
All four SPI status registers have Read Access and are default to "0" after power-on or hard reset.
Table 29: SPI Status Register 0
Address
04h
Content
Access
Reset
Data
Bit 7
R
0
PAR
Status Register 0 (SR0)
Structure
Bit 6
Bit 5
Bit 4
Bit 3
R
R
R
R
0
0
0
0
TW CPfail WD⁽¹⁾ OPENX
Bit 2
R
0
OPENY
Bit 1
R
0
-
Bit 0
R
0
-
Where:
R
Reset
PAR
TW
Cpfail
WD
OPENX
OPENY
Read only mode access
Status after power-on or hard reset
Parity check
Thermal warning
Charge pump failure
Watchdog event
Open Coil X detected
Open Coil Y detected
Remark: WD⁽¹⁾ – This bit indicates that the watchdog timer has not been cleared properly. If the master reads that WD is set to “1”
after reset, it means that a watchdog reset occurred (warm boot) instead of POR (cold boot). WD bit will be
cleared only when the master writes “0” to WDEN bit. (Table 14).
Data is not latched
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