AMIS-30522 Datasheet, PDF (21/29 Pages) AMI SEMICONDUCTOR – Micro-stepping Motor Driver

AMIS-30522
Registers are updated with the internal
status at the rising edge of CS
CS
Registers are updated with the internal status at the rising
edge of the internal AMIS-30521 clock when CS = 1
COMMAND
DATA
COMMAND
DI
WRITE DATA to ADDR2
NEW DATA for ADDR2
READ DATA from ADDR2
COMMAND or DUMMY
DATA from previous command or
NOT VALID after POR or RESET
DATA
DO
OLD DATA or NOT VALID
DATA
OLD DATA from ADDR2
DATA
OLD DATA from ADDR2
DATA
NEW DATA from ADDR2
Figure 21: A WRITE operation where DATA from the Master is written in SPI register with Address 2
followed by a READ back operation to confirm a correct WRITE operation
PC20080630.4
Note: The internal data-out shift buffer of AMIS-30521 is updated with the content of the selected SPI register only at the
last (every eight) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for
transmission cannot be written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might
represent old data.
Rev. 2 | Page 21 of 29 | www.onsemi.com