AMIS-30522 Datasheet, PDF (18/29 Pages) AMI SEMICONDUCTOR – Micro-stepping Motor Driver

AMIS-30522
9.0 SPI Interface
The serial peripheral interface (SPI) allows an external microcontroller (Master) to communicate with AMIS-30521. The
implemented SPI block is designed to interface directly with numerous micro-controllers from several manufacturers. AMIS-30521
acts always as a Slave and can’t initiate any transmission. The operation of the device is configured and controlled by means of
SPI registers which are observable for read and/or write from the Master.
9.1 SPI Transfer Format and Pin Signals
During a SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line
(CLK) synchronizes shifting and sampling of the information on the two serial data lines (DO and DI). DO signal is the output from
the Slave (AMIS-30521), and DI signal is the output from the Master. A chip select line (CSB) allows individual selection of a Slave
SPI device in a multiple-slave system. The CSB line is active low. If AMIS-30521 is not selected, DO is pulled up with the external
pull up resistor. Since AMIS-30521 operates as a Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks data out on the falling
edge and samples data in on rising edge of clock. The Master SPI port must be configured in MODE 0 too, to match this operation.
The SPI clock idles low between the transferred bytes. The diagram below is both a Master and a Slave timing diagram since CLK,
DO and DI pins are directly connected between the Master and the Slave.
# CLK cycle
CS
1
2
3
4
5
6
7
8
CLK
DI
MSB
6
5
4
3
2
1
LSB
DO
MSB
6
5
4
3
2
1
LSB
PC20080630.5
Figure 16: Timing Diagram of a SPI transfer
Note: At the falling edge of the eight clock pulse the data-out shift register is updated with the content of the addressed
internal SPI register. The internal SPI registers are updated at the first rising edge of the AMIS-30521 system clock when
CSB = High
9.2 Transfer packet:
Serial data transfer is assumed to follow MSB first rule. The transfer packet contains one or more bytes.
Figure 17: SPI transfer packet
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