AMIS-30522 Datasheet, PDF (14/29 Pages) AMI SEMICONDUCTOR – Micro-stepping Motor Driver

AMIS-30522
The following drawing illustrates the operation of the SLA-pin and the transparency-bit. "PWMsh" and "Icoil=0" are internal signals
that define together with SLAT the sampling and hold moments of the coil voltage.
VCOIL
div2
div4
Ssh
Sh
Csh
buf
Ch
SLA-pin
Icoil=0
PWMsh
PWMsh
Icoil=0
SLAT
VCOIL
SLAT
NOT(Icoil=0)
SLA-pin
last sample
is retained
VBEMF
t
retain last sample
SLAT=1 => SLA-pin is "transparent" during
V_BEMF sampling @ Coil Current Zero
Crossing. SLA-pin is updated "real-time".
previous output is kept at SLA pin
t
SLAT=0 => SLA-pin is not "transparent" during
V_BEMF sampling @ Coil Current Zero Crossing.
SLA-pin is updated when leaving current-less state.
PC20070604.8
Figure 13: Timing Diagram of SLA-pin
8.6 Warning, Error Detection and Diagnostics Feedback
8.6.1. Thermal Warning and Shutdown
When junction temperature rises above T_TW, the thermal warning bit <TW> is set (Table 29). If junction temperature increases
above thermal shutdown level, then the circuit goes in “Thermal Shutdown” mode (<TSD>) and all driver transistors are disabled
(high impedance) (Table 31). The conditions to reset flag <TSD> is to be at a temperature lower than T_TW and to clear the <TSD>
flag by reading it using any SPI read command.
8.6.2. Over-Current Detection
The over-current detection circuit monitors the load current in each activated output stage. If the load current exceeds the over-current detection
threshold, then the over-current flag is set and the drivers are switched off to reduce the power dissipation and to protect the integrated circuit.
Each driver transistor has an individual detection bit in
Table 30 and (Table 31(<OVCXij> and <OVCYij>). Error condition is latched and the microcontroller needs to clean the status
bits to reactivate the drivers.
8.6.3. Open Coil Detection
Open coil detection is based on the observation of 100 percent duty cycle of the PWM regulator. If in a coil 100 percent duty cycle
is detected for longer than 200ms then the related driver transistors are disabled (high-impedance) and an appropriate bit in the SPI
status register is set (<OPENX> or <OPENY>). (Table 29)
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