AMIS-30522 Datasheet, PDF (17/29 Pages) AMI SEMICONDUCTOR – Micro-stepping Motor Driver

AMIS-30522
8.10 CLR pin (=Hard Reset)
Logic 0 on CLR pin allows normal operation of the chip. To reset the complete digital inside AMIS-30522, the input CLR needs to
be pulled to logic 1 during minimum time given by T_CLR. (Table 6). This reset function clears all internal registers without the need of
a power-cycle. The operation of all analog circuits is depending on the reset state of the digital, charge pump remains active. Logic
0 on CLR pin resumes normal operation again.
The voltage regulator remains functional during and after the reset and the PORB/WD pin is not activated. Watchdog function is
reset completely.
8.11 Sleep Mode
The bit <SLP> in Table 17 is provided to enter a so-called “sleep mode”. This mode allows reduction of current-consumption when
the motor is not in operation. The effect of sleep mode is as follows:
• The drivers are put in HiZ
• All analog circuits are disabled and in low-power mode
• All internal registers are maintaining their logic content
• NXT and DIR inputs are forbidden
• SPI communication remains possible (slight current increase during SPI communication)
• Reset of chip is possible through CLR pin
• Oscillator and digital clocks are silent, except during SPI communication
The voltage regulator remains active but with reduced current-output capability (I_LOADSLP). The watchdog timer stops running and it’s
value is kept in the counter. Upon leaving sleep mode, this timer continues from the value it had before entering sleep mode.
Normal operation is resumed after writing logic ‘0’ to bit <SLP>. A start-up time is needed for the charge pump to stabilize. After this
time, NXT commands can be issued.
Rev. 2 | Page 17 of 29 | www.onsemi.com