AMIS-30522 Datasheet, PDF (22/29 Pages) AMI SEMICONDUCTOR – Micro-stepping Motor Driver

AMIS-30522
9.3 SPI Control Registers
All SPI control registers have Read/Write Access and default to "0" after power-on or hard reset.
Table 14: SPI Control Register WR
Control Register (WR)
Address _Content
Bit 7
Bit 6 Bit 5
Structure
Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Access
R/W R/W R/W R/W R/W R/W R/W R/W
00h
Reset
0
0
0
0
0
0
0
0
Data
WDEN
WDT[3:0]
-
-
-
Where:
R/W
Read and Write access
Reset:
Status after power-On or hard reset
WDEN:
Watchdog enable. Writing “1” to this bit will activate the watchdog timer (if not enabled yet) or will clear this timer
(if already enabled). Writing “0” to this bit will clear WD bit (Table 29).
WDT[3:0]: Watchdog timeout interval
Table 15: SPI Control Register 0
Control Register 0 (CR0)
Address _Content
Bit 7
Structure
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
01h
Access
Reset
R/W R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
0
Data
SM[2:0]
CUR[4:0]
Where:
R/W
Read and Write access
Reset:
Status after power-On or hard reset
SM[2:0]: Step mode
CUR[4:0]: Current amplitude
Bit 0
R/W
0
Table 16: SPI Control Register 1
Control Register 1 (CR1)
Address _Content
Bit 7
Bit 6
Bit 5
Structure
Bit 4 Bit 3
Access
R/W
R/W R/W R/W R/W
02h
Reset
0
0
0
0
0
Data
DIRCTRL NXTP -
- PWMF
Where:
R/W
Read and Write access
Reset::
Status after power-On or hard reset
DIRCTRL Direction control
NXTP
NEXT polarity
PWMF
PWM frequency
PWMJ
PWM jitter
EMC[1:0] EMC slope control
Bit 2
R/W
0
PWMJ
Bit 1
Bit 0
R/W R/W
0
0
EMC[1:0]
Table 17: SPI Control Register 2
Control Register 2 (CR2)
Address _Content
Bit 7
Bit 6 Bit 5
Structure
Bit 4 Bit 3
Access
R/W R/W R/W R/W R/W
03h
Reset
0
0
0
0
0
Data
MOTEN SLP SLAG SLAT -
Where:
R/W
Read and Write access
Reset:
Status after power-On or hard reset
MOTEN
Motor enable
SLP
Sleep
SLAG
Speed load angle gain
SLAT
Speed load angle transparency
Bit 2
R/W
0
-
Bit 1
R/W
0
-
Bit 0
R/W
0
-
Rev. 2 | Page 22 of 29 | www.onsemi.com