TCC-202 Datasheet, PDF (19/23 Pages) ON Semiconductor – Two-Output PTIC Control IC

TCC−202
Table 16. RFFE COMMAND FRAME for Extended Register Write Command Sequence for DACs Loading Procedure
Description
SSC
Command Frame
<byte count>
Extended Register Wrrittee DAC A&BB&&CC
1 0 SA (3,0) 0 0 0 0 0 0 0 1 0 P
<starting address>
000000 01P
Data Frame
TC(7:0)
P
DAC A (6:0)
P
DAC_B (6:0)
P BP
Register Read Command Sequence
MIPI−RFFE Read operation can access RFFE_STATUS register from TCC−202 device address 0x1A. Extended Register
Read command sequence is not supported.
Configuration Settings
Table 17. DAC CONFIGURATION (ENABLE MASK) at [0x00] Defaults shown as (x)
Bit 6 (1)
Bit 5 (0)
Bit 4 (0)
Bit 3 (0)
Bit 2 (0)
Bit 1 (0)
Bit 0 (0)
SSE
reserved
reserved
DAC A
DAC B
reserved
reserved
SSE = 0 spread spectrum disabled, SSE = 1 spread spectrum enabled (default), this controls the average boost clock which is
nominally 2 MHz and spread between 0.8 MHz and 3.2 MHz when enabled (default).
Table 18. DAC MODE SETUP: DAC ENABLE
Bit3
Bit2
DAC A
0
0
Off
0
1
Off
1
0
Enabled
1
1
Enabled
DAC B
Off
Enabled
Off
Enabled
(Default)
Table 19. BOOST DAC MODE SETUP (VHV) at [0x10] (Notes 13, 14)
Bit 7*
Bit 6*
Bit 5*
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
1
0
0
0
1
0
1
1
0
0
0
0
1
0
1
1
1
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
1
0
1
0
0
0
0
1
1
0
1
1
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
13. Bit 4 is fixed at logic 1 for reverse software compatibility
14. VHV is recommended to be set at VDac Max + 2V for non−turbo operation and + 4V when turbo is used.
* Indicates reserved bits
VHV (V)
13
14
15
16
17
18
19
20
21
22
23
24 (Default)
25
26
27
28
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