TCC-202 Datasheet, PDF (15/23 Pages) ON Semiconductor – Two-Output PTIC Control IC

TCC−202
Register RFFE:
RFFE_GROUP_SID_0x1B
Address RFFE A[4:0]:
Reset Source: nreset_dig or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
6
5
4
3
2
1
Bits
Reserved Reserved Reserved Reserved
GSID[3]
GSID[2]
GSID[1]
Reset
0
0
0
0
W−0
W−0
W−0
GSID = Group Slave Identifier Register
NOTE:
NOTE:
NOTE:
NOTE:
NOTE:
The GSID[3:0] field can be written directly by messages using USID.
GSID value is NOT retained during SHUTDOWN power mode.
GSID value is not affected by SWR bit from RFFE_STATUS register
Frames using USID = GSID, can write only to RFFE_REG_0x1C[7:6] and [2:0].
RFFE READ frames containing GSID will be ignored
0x1B
0
GSID[0]
W−0
Register RFFE:
RFFE_REG_0x1C
Address RFFE A[4:0]:
0x1C
Reset Source: nreset_dig or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
6
5
4
3
2
1
0
Bits
Power Mode
Trigger Mask 2
Trigger Mask 1
Trigger Mask 0
Trigger 2 Trigger 1 Trigger 0
(Note 12)
(Notes 8, 9, 10, 11) (Notes 8, 9, 10, 11) (Notes 8, 9, 10, 11)
Reset
W−0
W−0
W−0
W−0
W−0
W−0
W−0
W−0
8. Trigger Mask bits [5:3] can be changed, either set or cleared, only with an individual message using USID
9. During broadcast MIPI−RFFE accesses using GSID = ‘0000’, Trigger bits [2:0] are masked by the pre−existent setting of Trigger Mask Bits
[5:3]
10. During Individual MIPI−RFFE accesses using USID, Trigger bits [2:0] are masked by the incoming Trigger Mask bits [5:3] within the same
write message to RFFE_REG_0x1C register. During Individual MIPI−RFFE accesses using USID, pre−existent setting of Trigger Mask Bits
[5:3] is ignored.
11. When RFFE_REG_0x1C/ Trigger_Mask_2 = ‘1’ and Trigger_Mask_1 = ‘1’ and Trigger_Mask_0 = ‘1’, then DAC messages will be sent to
DACs immediately after RFFE_REG_0x04 is received, without waiting for any trigger
12. Power mode field bits [7:6] and Triggers bits [2:0] can be changed by either MIPI−RFFE broadcast messages when USID field within the
Register Write Command is 0x0 , or individual messages when USID fields within the Register Write Command is equal with
RFFE_REG_0x1F[3:0]
NOTE: All the 8 bits of RFFE_REG_0x1C register bits are NOTaffected by SWR bit from RFFE_STATUS register
Bit [7:6]: Power Mode
00: ACTIVE mode, defined by following hardware behavior:
• Boost Control active, VHV set by Digital Interface
• Vout A and B enabled and controlled by Digital Interface
01: STARTUP mode, defined by following hardware behavior: o
• Boost Control active, VHV set by Digital Interface
• Vout A and B disabled
10: LOW POWER mode is defined by following hardware behavior:
• Digital interface is active, while all other circuits are in lowpower mode
11: Reserved (State of hardware does not change)
Bit 5: Mask trigger 2
0:Trigger 2 not masked. Data goes to destination register after bit 2 is written value 1 (default)
1:Trigger 2 is masked. Data goes directly to the destination register
Bit 4: Mask trigger 1
0:Trigger 1 not masked. Data goes to destination register after bit 1 is written value 1(default)
1:Trigger 1 is masked. Data goes directly to the destination register.
Bit 3: Mask trigger 0
0:Trigger 0 not masked. Data goes to destination register after bit 0 is written value 1(default)
1:Trigger 0 is masked. Data goes directly to the destination register.
Bit 2: Trigger 2
Write 1 to this bit, to move data from shadowregisters into destination register. This trigger can be masked by bit 5.
Bit 1: Trigger 1
Write 1 to this bit, to move data from shadowregisters into destination register. This trigger can be masked by bit 4.
Bit 0: Trigger 0
Write 1 to this bit, to move data from shadowregisters into destination register. This trigger can be masked by bit 3.
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