TCC-202 Datasheet, PDF (14/23 Pages) ON Semiconductor – Two-Output PTIC Control IC

TCC−202
Register RFFE:
RFFE_REG_0x10
Address RFFE A[4:0]:
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
6
5
4
3
2
1
Bits
Reserved
Fixed
Boost voltage value
Reset
U−0
U−0
U−0
U−1
W-1
W−0
W-1
Bit [3:0]: Boost voltage value
0x10
0
W-1
Register RFFE:
RFFE_STATUS_0x1A
Address RFFE A[4:0]:
0x1A
Reset Source: nreset_dig or SWR = ‘1’ or PWR_MODE = ‘01’ (transition through STARTUP mode)
7
6
5
4
3
2
1
0
Bits
SWR
CFPE
CLE
AFPE
DFPE
RURE
WURE
BGE
Reset
W−0
R−0
R−0
R−0
R−0
R−0
R−0
R−0
RFFE_STATUS register can be read any time after power−up without the need to enable the Read Operation as described
below.
SWR Soft−Reset MIPI−RFFE registers
Write ‘1’ to this bit to reset all the MIPI−RFFE registers, except RFFE_REG_0x1C, RFFE_USID, and RFFE_GROUP_SID
This bit will always Read−back ‘0’.
The soft reset occurs in the last clock cycle of the MIPI−RFFE frame which Writes ‘1’ to this bit.
Right immediately after this frame, all the MIPI−RFFE registers have the reset value and are ready to be reprogrammed as
desired.
The OTP duplicated registers are reset to the values written in OTP.
SWR can be written only by USID messages. GSID and Broadcast frames will be ignored when writing to this register field.
RFFE_STATUS Bits [6:0] are set ‘1’ by hardware to flag when a certain condition is detected, as described below.
RFFE_STATUS Bits [6:0] cannot be written, but it is cleared to ‘0’ under following conditions:
• Hardware Self−reset is applied after RFFE_STATUS is READ
• When SWR is written ‘1’ with USID frames
• When power mode transitions through STARTUP mode ‘01’
• After Power−up Reset
CFPE
1: Command frame with parity error received.
On the occurrence of this error, the slave will ignore the entire Command Sequence
CLE
1: Incompatible command length, due to unexpected SSC received before command length to be completed.
On the occurrence of this error, the slave will accept Write data up to the last correct and complete frame. When MIPI−RFFE
multi−byte Read command is detected, the slave will always replay with an extended Read command of length of one byte.
AFPE
1: Address frame with parity error received.
On the occurrence of this error, the slave will ignore the entire Command Sequence
DFPE
1: Data frame with parity error received.
On the occurrence of this error, the slave will ignore only the erroneous data byte (s)
RURE
1: Read of non−existent register was detected.
On the occurrence of this error, the slave will not respond to the Read command frame.
When the Read Operation is not enabled ,any read from an address other than 0x1A, will set RURE and the slave will not
respond to the Read command frame.
When the Read Operation is enabled , any read from an unoccupied RFFE register address will set RURE.
WURE
1: Write to non−existent register was detected.
On the occurrence of this error, the slave discards data being written, and on the next received frame, proceeds as normal
BGE
1: Read using the Broadcast ID was detected
On the occurrence of this error, the slave will ignore the entire Command Sequence
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