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COP688CL Datasheet, PDF (9/40 Pages) National Semiconductor (TI) – General Description
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DC Electrical Characteristics b55 C s TA s a25 C unless otherwise specified (Continued)
Parameter
Conditions
Min
Typ
Max
Units
Allowable Sink Source
Current per Pin
D Outputs (Sink)
All others
12
mA
25
mA
Maximum Input Current
without Latchup (Note 4)
150
mA
RAM Retention Voltage Vr
500 ns Rise
20
V
and Fall Time (Min)
Input Capacitance
7
pF
Load Capacitance on D2
1000
pF
Note 1 Rate of voltage change must be less then 0 5 V ms
Note 2 Supply current is measured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open
Note 3 The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations Test conditions All inputs tied to VCC L and G ports in the TRI-
STATE mode and tied to ground all outputs low and tied to ground The Clock Monitor and the comparators are disabled
AC Specifications for COP688CL
AC Electrical Characteristics b55 C s TA s a125 C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (tc)
Crystal Resonator or
External Oscillator
R C Oscillator (div-by 10)
VCC t 4 5V
1
VCC t 4 5V
3
Inputs
tSETUP
tHOLD
VCC t 4 5V
200
VCC t 4 5V
60
Output Propagation Delay (Note 5)
tPD1 tPD0
SO SK
All Others
RL e 2 2k CL e 100 pF
VCC t 4 5V
VCC t 4 5V
MICROWIRE Setup Time (tUWS)
20
MICROWIRE Hold Time(tUWH)
56
MICROWIRE Output Propagation Delay (tUPD)
Input Pulse Width
Interrupt Input High Time
1
Interrupt Input Low Time
1
Timer Input High Time
1
Timer Input Low Time
1
Reset Pulse Width
1
DC
ms
DC
ms
ns
ns
07
ms
1
ms
ns
ns
220
ns
tc
tc
tc
tc
ms
Note 4 Pins G6 and RESET are designed with a high voltage input network for factory testing These pins allow input voltages greater than VCC and the pins will
have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC) The effective
resistance to VCC is 750X (typical) These two pins will not latch up The voltage at the pins must be limited to less than 14V
Note 5 The output propagation delay is referenced to the end of the instruction cycle where the output change occurs
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