COP688CL Datasheet, PDF (17/40 Pages) National Semiconductor (TI) – General Description

Timers (Continued)
Mode 3 Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block Tx in the
input capture mode
In this mode the timer Tx is constantly running at the fixed
t_c rate The two registers RxA and RxB act as capture
registers Each register acts in conjunction with a pin The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin Control bits
TxC3 TxC2 and TxC1 allow the trigger events to be speci-
fied either as a positive or a negative edge The trigger con-
dition for each input pin can be specified independently
The trigger conditions can also be programmed to generate
interrupts The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags TxPNDA and TxPNDB The control flag TxE-
NA allows the interrupt on TxA to be either enabled or dis-
abled Setting the TxENA flag enables interrupts to be gen-
erated when the selected trigger condition occurs on the
TxA pin Similarly the flag TxENB controls the interrupts
from the TxB pin
Underflows from the timer can also be programmed to gen-
erate interrupts Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer under-
flow interrupt pending flag in the Input Capture mode) Con-
sequently the TxC0 control bit should be reset when enter-
ing the Input Capture mode The timer underflow interrupt is
enabled with the TxENA control flag When a TxA interrupt
occurs in the Input Capture mode the user must check both
the TxPNDA and TxC0 pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt
Figure 9 shows a block diagram of the timer in Input Capture
mode
TIMER CONTROL FLAGS
The timers T1 and T2 have indentical control structures
The control bits and their functions are summarized below
TxC0
Timer Start Stop control in Modes 1 and 2
(Processor Independent PWM and External
Event Counter) where 1 e Start 0 e Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)
TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag
TxENA
TxENB
Timer Interrupt Enable Flag
Timer Interrupt Enable Flag
1 e Timer Interrupt Enabled
0 e Timer Interrupt Disabled
TxC3
TxC2
TxC1
Timer mode control
Timer mode control
Timer mode control
FIGURE 9 Timer in Input Capture Mode
TL DD 9766 – 15
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