COP688CL Datasheet, PDF (27/40 Pages) National Semiconductor (TI) – General Description

Memory Map
All RAM ports and registers (except A and PC) are mapped
into data memory address space
Address
Contents
00 to 6F On-Chip RAM bytes
70 to BF Unused RAM Address Space
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD to CF
Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA Lower Byte
Timer T2 Autoload Register T2RA Upper Byte
Timer T2 Autoload Register T2RB Lower Byte
Timer T2 Autoload Register T2RB Upper Byte
Timer T2 Control Register
WATCHDOG Service Register (Reg WDSVR)
MIWU Edge Select Register (Reg WKEDG)
MIWU Enable Register (Reg WKEN)
MIWU Pending Register (Reg WKPND)
Reserved
Reserved
Reserved
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD to DF
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port D Data Register
Reserved for Port D
E0 to E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
Reserved
Timer T1 Autoload Register T1RB Lower Byte
Timer T1 Autoload Register T1RB Upper Byte
ICNTRL Register
MICROWIRE Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1RA Lower Byte
Timer T1 Autoload Register T1RA Upper Byte
CNTRL Control Register
PSW Register
F0 to FB
FC
FD
FE
FF
On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
Reserved
Reading memory locations 70-7F Hex will return all ones Reading other
unused memory locations will return undefined data
Addressing Modes
The device has ten addressing modes six for operand ad-
dressing and four for transfer of control
OPERAND ADDRESSING MODES
Register Indirect
This is the ‘‘normal’’ addressing mode The operand is the
data memory addressed by the B pointer or X pointer
Register Indirect (with auto post increment or
decrement of pointer)
This addressing mode is used with the LD and X instruc-
tions The operand is the data memory addressed by the B
pointer or X pointer This is a register indirect mode that
automatically post increments or decrements the B or X reg-
ister after executing the instruction
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand
Immediate
The instruction contains an 8-bit immediate field as the op-
erand
Short Immediate
This addressing mode is used with the Load B Immediate
instruction The instruction contains a 4-bit immediate field
as the operand
Indirect
This addressing mode is used with the LAID instruction The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory
TRANSFER OF CONTROL ADDRESSING MODES
Relative
This mode is used for the JP instruction with the instruction
field being added to the program counter to get the new
program location JP has a range from b31 to a32 to allow
a 1-byte relative jump (JP a 1 is implemented by a NOP
instruction) There are no ‘‘pages’’ when using JP since all
15 bits of PC are used
Absolute
This mode is used with the JMP and JSR instructions with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC) This allows jumping to any loca-
tion in the current 4k program memory segment
Absolute Long
This mode is used with the JMPL and JSRL instructions
with the instruction field of 15 bits replacing the entire 15
bits of the program counter (PC) This allows jumping to any
location in the current 4k program memory space
Indirect
This mode is used with the JID instruction The contents of
the accumulator are used as a partial address (lower 8 bits
of PC) for accessing a location in the program memory The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruc-
tion
Note
The VIS is a special case of the Indirect Transfer of Control address-
ing mode where the double byte vector associated with the interrupt
is transferred from adjacent addresses in the program memory into
the program counter (PC) in order to jump to the associated interrupt
service routine
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