COP688CL Datasheet, PDF (7/40 Pages) National Semiconductor (TI) – General Description

DC Electrical Characteristics b40 C ^s T_A ^s a85 C unless otherwise specified (Continued)
Parameter
Conditions
Min
Typ
Max
Allowable Sink Source
Current per Pin
D Outputs (Sink)
15
All others
3
Maximum Input Current
without Latchup (Note 4)
T_A e 25 C
g100
RAM Retention Voltage V_r
500 ns Rise
2
and Fall Time (Min)
Input Capacitance
7
Load Capacitance on D2
1000
Units
mA
mA
mA
V
pF
pF
AC Electrical Characteristics b40 C ^s T_A ^s a85 C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (t_c)
Crystal or Resonator
R C Oscillator
4V ^s V_CC ^s 6V
1
2 5V ^s V_CC ^k 4V
25
4V ^s V_CC ^s 6V
3
2 5V ^s V_CC ^k 4V
75
Inputs
t_SETUP
t_HOLD
4V ^s V_CC ^s 6V
200
2 5V ^s V_CC ^k 4V
500
4V ^s V_CC ^s 6V
60
2 5V ^s V_CC ^k 4V
150
Output Propagation Delay (Note 5)
t_PD1 t_PD0
SO SK
All Others
R_L e 2 2k C_L e 100 pF
4V ^s V_CC ^s 6V
2 5V ^s V_CC ^k 4V
4V ^s V_CC ^s 6V
2 5V ^s V_CC ^k 4V
MICROWIRE Setup Time (t_UWS)
20
MICROWIRE Hold Time (t_UWH)
56
MICROWIRE Output Propagation Delay (t_UPD)
Input Pulse Width
Interrupt Input High Time
1
Interrupt Input Low Time
1
Timer Input High Time
1
Timer Input Low Time
1
Reset Pulse Width
1
DC
ms
DC
ms
DC
ms
DC
ms
ns
ns
ns
ns
07
ms
1 75
ms
1
ms
25
ms
ns
ns
220
ns
t_c
t_c
t_c
t_c
ms
Note 4 Pins G6 and RESET are designed with a high voltage input network for factory testing These pins allow input voltages greater than V_CC and the pins will
have sink current to V_CC when biased at voltages greater than V_CC (the pins do not have source current when biased at a voltage below V_CC) The effective
resistance to V_CC is 750X (typical) These two pins will not latch up The voltage at the pins must be limited to less than 14V
Note 5 The output propagation delay is referenced to the end of the instruction cycle where the output change occurs
7
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