COP688CL Datasheet, PDF (14/40 Pages) National Semiconductor (TI) – General Description

Control Registers (Continued)
T1C0
Timer T1 Start Stop control in timer
modes 1 and 2
Timer T1 Underflow Interrupt Pending Flag in
timer mode 3
T1C1
Timer T1 mode control bit
T1C2
Timer T1 mode control bit
T1C3
Timer T1 mode control bit
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0
Bit 7
Bit 0
PSW Register (Address X 00EF)
The PSW register contains the following select bits
GIE
Global interrupt enable (enables interrupts)
EXEN Enable external interrupt
BUSY MICROWIRE PLUS busy shifting flag
EXPND External interrupt pending
T1ENA Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
in mode 1 T1 Underflow in Mode 2 T1A cap-
ture edge in mode 3)
C
Carry Flag
HC
Half Carry Flag
HC C T1PNDA T1ENA EXPND BUSY EXEN GIE
Bit 7
Bit 0
The Half-Carry bit is also affected by all the instructions that
affect the Carry flag The SC (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the car-
ry flags In addition to the SC and RC instructions ADC
SUBC RRC and RLC instructions affect the carry and Half
Carry flags
ICNTRL Register (Address X 00E8)
The ICNTRL register contains the following bits
T1ENB Timer T1 Interrupt Enable for T1B Input capture
edge
T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-
ture edge
mWEN Enable MICROWIRE PLUS interrupt
mWPND MICROWIRE PLUS interrupt pending
T0EN Timer T0 Interrupt Enable (Bit 12 toggle)
T0PND Timer T0 Interrupt pending
LPEN L Port Interrupt Enable (Multi-Input Wakeup In-
terrupt)
Bit 7 could be used as a flag
Unused LPEN T0PND T0EN mWPND mWEN T1PNDB T1ENB
Bit 7
Bit 0
T2CNTRL Register (Address X 00C6)
The T2CNTRL register contains the following bits
T2ENB Timer T2 Interrupt Enable for T2B Input capture
edge
T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-
ture edge
T2ENA Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA
in mode 1 T2 Underflow in mode 2 T2A cap-
ture edge in mode 3)
T2C0
Timer T2 Start Stop control in timer modes 1
and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3
T2C1 Timer T2 mode control bit
T2C2 Timer T2 mode control bit
T2C3 Timer T2 mode control bit
T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB
Bit 7
Bit 0
Timers
The device contains a very versatile set of timers (T0 T1
T2) All timers and associated autoreload capture registers
power up containing random data
Figure 6 shows a block diagram for the timers
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