COP688CL Datasheet, PDF (18/40 Pages) National Semiconductor (TI) – General Description

Timers (Continued)
The timer mode control bits (TxC3 TxC2 and TxC1) are detailed below
TxC3
TxC2
TxC1
Timer Mode
Interrupt A
Source
0
0
0
MODE 2 (External
Timer
Event Counter)
Underflow
0
0
1
MODE 2 (External
Timer
Event Counter)
Underflow
1
0
1
MODE 1 (PWM)
Autoreload
TxA Toggle
RA
1
0
0
MODE 1 (PWM)
Autoreload
No TxA Toggle
RA
0
1
0
MODE 3 (Capture)
Pos TxA
Captures
Edge or
TxA Pos Edge
Timer
TxB Pos Edge
Underflow
1
1
0
MODE 3 (Capture)
Pos TxA
Captures
Edge or
TxA Pos Edge
Timer
TxB Neg Edge
Underflow
0
1
1
MODE 3 (Capture)
Neg TxB
Captures
Edge or
TxA Neg Edge
Timer
TxB Pos Edge
Underflow
1
1
1
MODE 3 (Capture)
Neg TxA
Captures
Edge or
TxA Neg Edge
Timer
TxB Neg Edge
Underflow
Interrupt B
Source
Pos TxB
Edge
Pos TxB
Edge
Autoreload
RB
Autoreload
RB
Pos TxB
Edge
Neg TxB
Edge
Pos TxB
Edge
Neg TxB
Edge
Timer
Counts On
TxA
Pos Edge
TxA
Neg Edge
t_c
t_c
t_c
t_c
t_c
t_c
Power Save Modes
The device offers the user two power save modes of opera-
tion HALT and IDLE In the HALT mode all microcontroller
activities are stopped In the IDLE mode the on-board oscil-
lator circuitry and timer T0 are active but all other microcon-
troller activities are stopped In either mode all on-board
RAM registers I O states and timers (with the exception of
T0) are unaltered
HALT MODE
The device is placed in the HALT mode by writing a ‘‘1’’ to
the HALT flag (G7 data bit) All microcontroller activities
including the clock timers are stopped The WATCHDOG
logic is disabled during the HALT mode However the clock
monitor circuitry if enabled remains active and will cause
the WATCHDOG output pin (WDOUT) to go low If the
HALT mode is used and the user does not want to activate
the WDOUT pin the Clock Monitor should be disabled after
the device comes out of reset (resetting the Clock Monitor
control bit with the first write to the WDSVR register) In the
HALT mode the power requirements of the device are mini-
mal and the applied voltage (V_CC) may be decreased to V_r
(V_r e 2 0V) without altering the state of the machine
The device supports three different ways of exiting the
HALT mode The first method of exiting the HALT mode is
with the Multi-Input Wakeup feature on the L port The sec-
ond method is with a low to high transition on the CKO (G7)
pin This method precludes the use of the crystal clock con-
figuration (since CKO becomes a dedicated output) and so
may be used with an RC clock configuration The third
method of exiting the HALT mode is by pulling the RESET
pin low
Since a crystal or ceramic resonator may be selected as the
oscillator the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full ampli-
tude and frequency stability The IDLE timer is used to gen-
erate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution In this case
upon detecting a valid Wakeup signal only the oscillator
circuitry is enabled The IDLE timer is loaded with a value of
256 and is clocked with the t_c instruction cycle clock The t_c
clock is derived by dividing the oscillator clock down by a
factor of 10 The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE timer is clocked only
when the oscillator has a sufficiently large amplitude to
meet the Schmitt trigger specifications This Schmitt trigger
is not part of the oscillator closed loop The startup timeout
from the IDLE timer enables the clock signals to be routed
to the rest of the chip
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