COP688CL Datasheet, PDF (12/40 Pages) National Semiconductor (TI) – General Description

Pin Descriptions (Continued)
Port G has the following dedicated functions
G1 WDOUT WATCHDOG and or Clock Monitor
dedicated output
G7 CKO Oscillator dedicated output or general
purpose input
Port C is an 8-bit I O port The 40-pin device does not have
a full complement of Port C pins The unavailable pins are
not terminated A read operation for these unterminated
pins will return unpredictable values
Port I is an 8-bit Hi-Z input port The 40-pin device does not
have a full complement of Port I pins Pins 15 and 16 on this
package must be connected to GND
The 28-pin device has four I pins (I0 I1 I4 I5) The user
should pay attention when reading port I to the fact that I4
and I5 are in bit positions 4 and 5 rather than 2 and 3
The unavailable pins (I4–I7) are not terminated i e they are
floating A read operation for these unterminated pins will
return unpredictable values The user must ensure that the
software takes into account by either masking or restricting
the accesses to bit operations The unterminated port I pins
will draw power only when addressed
Port D is an 8-bit output port that is preset high when RE-
SET goes low The user can tie two or more D port outputs
(except D2) together in order to get a higher drive
Note Care must be exercised with the D2 pin operation At RESET the
external loads on this pin must ensure that the output voltages stay
above 0 8 V_CC to prevent the chip from entering special modes Also
keep the external loading on D2 to less than 1000 pF
Functional Description
The architecture of the device is modified Harvard architec-
ture With the Harvard architecture the control store pro-
gram memory (ROM) is separated from the data store mem-
ory (RAM) Both ROM and RAM have their own separate
addressing space with separate address buses The archi-
tecture though based on Harvard architecture permits
transfer of data from ROM to RAM
CPU REGISTERS
The CPU can do an 8-bit addition subtraction logical or
shift operation in one instruction (t_c) cycle time
There are five CPU registers
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer which can be optionally
post auto incremented or decremented
X is an 8-bit alternate RAM address pointer which can be
optionally post auto incremented or decremented
SP is the 8-bit stack pointer which points to the subroutine
interrupt stack (in RAM) The SP is initialized to RAM ad-
dress 06F with reset
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC)
PROGRAM MEMORY
Program memory consists of 4096 bytes of ROM These
bytes may hold program instructions or constant data (data
tables for the LAID instruction jump vectors for the JID in-
struction and interrupt vectors for the VIS instruction) The
program memory is addressed by the 15-bit program coun-
ter (PC) All interrupts vector to program memory location
0FF Hex
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers the I O registers (Configuration Data
and Pin) the control registers the MICROWIRE PLUS SIO
shift register and the various registers and counters asso-
ciated with the timers (with the exception of the IDLE timer)
Data memory is addressed directly by the instruction or indi-
rectly by the B X and SP pointers
The device has 128 bytes of RAM Sixteen bytes of RAM
are mapped as ‘‘registers’’ at addresses 0F0 to 0FF Hex
These registers can be loaded immediately and also decre-
mented and tested with the DRSZ (decrement register and
skip if zero) instruction The memory pointer registers X SP
and B are memory mapped into this space at address loca-
tions 0FC to 0FE Hex respectively with the other registers
(other than reserved register 0FF) being available for gener-
al usage
The instruction set permits any bit in memory to be set
reset or tested All I O and registers (except A and PC) are
memory mapped therefore I O bits and register bits can be
directly and individually set reset and tested The accumu-
lator (A) bits can also be directly and individually tested
Note RAM contents are undefined upon power-up
Reset
The RESET input when pulled low initializes the microcon-
troller Initialization will occur whenever the RESET input is
pulled low Upon initialization the data and configuration
registers for Ports L G and C are cleared resulting in these
Ports being initialized to the TRI-STATE mode Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WATCHDOG and or Clock Monitor error
output pin Port D is initialized high with RESET The PC
PSW CNTRL ICNTRL and T2CNTRL control registers are
cleared The Multi-Input Wakeup registers WKEN WKEDG
and WKPND are cleared The Stack Pointer SP is initial-
ized to 06F Hex
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed and with both
the WATCHDOG service window bits set and the Clock
Monitor bit set The WATCHDOG and Clock Monitor detec-
tor circuits are inhibited during reset The WATCHDOG serv-
ice window bits are initialized to the maximum WATCHDOG
service window of 64k t_c clock cycles The Clock Monitor bit
is initialized high and will cause a Clock Monitor error fol-
lowing reset if the clock has not reached the minimum spec-
ified frequency at the termination of reset A Clock Monitor
error will cause an active low error output on pin G1 This
error output will continue until 16 – 32 t_c clock cycles follow-
ing the clock frequency reaching the minimum specified val-
ue at which time the G1 output will enter the TRI-STATE
mode
The external RC network shown in Figure 4 should be used
to ensure that the RESET pin is held low until the power
supply to the chip stabilizes
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