PC87317VUL Datasheet, PDF (82/272 Pages) National Semiconductor (TI) – PC87317VUL/PC97317VUL SuperI/O Plug and Play Compatible with ACPI Compliant Controller/Extender

Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Bit 2 - IRRX1 Status (IRRX1_S)
This bit is set to 1, when an IRRX1 event occurs, regard-
less of the IRRX1 Enable bit setting (bit 2 of the
GP1_EN0 and GP2_EN0 registers). IRRX1 Event is de-
fined by bits 2-0 of the APCR5 register.
Bit 3 - IRRX2 Status (IRRX2_S)
This bit is set to 1, when an IRRX2 event occurs, regard-
less of IRRX2 Enable bit (bit 3 of the GP1_EN0 and
GP2_EN0 registers). IRRX2 Event is defined by bits 5-
3 of the APCR5 register.
Note that if bit 3 of the GP1_EN0 register and bit 3 of the
GP2_EN0 register are both cleared to 0, spurious
IRRX2 events may be detected by this bit.
Bit 4 - GPIO12 Status (GPIO12_S)
This bit is set to 1, when a GPIO12 event occurs, re-
gardless of the GPIO12 Enable bit setting (bit 4 of the
GP1_EN0 and GP2_EN0 registers). GPIO12 Event is
defined by bits 2-0 of the APCR6 register.
Bit 5 - GPIO13 Status (GPIO13_S)
This bit is set to 1, when a GPIO13 event occurs, re-
gardless of the GPIO13 Enable bit setting (bit 5 of the
GP1_EN0 and GP2_EN0 registers). GPIO13 Event is
defined by bits 5-3 of the APCR6 register.
Bit 6 - GPIO10 Status (GPIO10_S)
This bit is set to 1, when a GPIO10 event occurs, re-
gardless of the GPIO10 Enable bit setting (bit 6 of the
GP1_EN0 and GP2_EN0 registers). GPIO10 Event is
defined by bits 7-5 of the APCR3 register.
Bit 7 - P12 Status (P12_S)
This bit is set to 1, when a P12 event occurs, regardless
of the P12 Enable bit setting (bit 7 of the GP1_EN0 and
GP2_EN0 registers). P12 Event is defined by bits 2-0 of
the APCR7 register. Note that P12 is multiplexed with
CS0. In any case, the internal P12 port’s output is de-
tected.
4.7.2 General Purpose 1 Status 1 Register
(GP1_STS1), Offset 01h
This register is reserved. Read returns 0.
4.7.3 General Purpose 1 Status 2 Register
(GP1_STS2), Offset 02h
This register is reserved. Read returns 0.
4.7.4 General Purpose 1 Status 3 Register
(GP1_STS3), Offset 03h
This register is reserved. Read returns 0.
4.7.5 General Purpose 1 Enable 0 Register
(GP1_EN0)
Upon first power Up, these bits are initialized to 0. Upon
Master Reset, bits 4 to 7 are reset to 0.
76543210
General Purpose 1
Enable 0 Register
0 0 0 0 0 0 0 0 ^Power-Up
Reset
Required
(GP1_EN0)
Offset 04h
PME1_E
PME2_E
IRRX1_E
IRRX2_E
GPIO12_E
GPIO13_E
GPIO10_E
P12_E
FIGURE 4-43. GP1_EN0 Register Bitmap
Bit 0 - PME1 Enable (PME1_E)
0: PME1 Status bit is ignored (bit 0 of the GP1_STS0
register).
1: When the PME1 Status bit is 1:
- Activate the ONCTL pin.
- Activate the SCI signal or the POR pin (according
to bit 0 of the PM1_CNT_LOW register).
When PME1 is not selected on its corresponding
pin, this bit should be 0.
Bit 1 - PME2 Enable (PME2_E)
0: PME2 Status bit is ignored (bit 1 of the GP1_STS0
register).
1: When the PME2 Status bit is 1:
- Activate the ONCTL pin.
- Activate the SCI signal or the POR pin (according
to bit 0 of the PM1_CNT_LOW register).
When PME2 is not selected on its corresponding
pin, this bit should be 0.
Bit 2 - IRRX1 Enable (IRRX1_E)
0: IRRX1 Status bit is ignored (bit 2 of the GP1_STS0
register).
1: When the IRRX1 Status bit is 1:
- Activate the ONCTL pin.
- Activate the SCI signal or the POR pin (according
to bit 0 of the PM1_CNT_LOW register).
When IRRX1 is not selected on its corresponding
pin, this bit should be 0.
Bit 3 - IRRX2 Enable (IRRX2_E)
0: IRRX2 Status bit is ignored (bit 3 of the GP1_STS0
register).
1: When the IRRX2 Status bit is 1:
- Activate the ONCTL pin.
- Activate the SCI signal or the POR pin (according
to bit 0 of the PM1_CNT_LOW register).
When IRRX2 is not selected on its corresponding
pin, this bit should be 0.
Bit 4 - GPIO12 Enable (GPIO12_E)
0: GPIO12 Status bit is ignored (bit 4 of the
GP1_STS0 register).
1: When the GPIO12 Status bit is 1:
- Activate the SCI signal or the POR pin (according
to bit 0 of the PM1_CNT_LOW register).
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