PC87317VUL Datasheet, PDF (204/272 Pages) National Semiconductor (TI) – PC87317VUL/PC97317VUL SuperI/O Plug and Play Compatible with ACPI Compliant Controller/Extender

Enhanced Serial Port - UART1 (Logical Device 6)
0: No transmission deferral enabled. (Default)
1: Transmission deferral enabled.
This bit is effective only if the Transmission FIFOs is en-
abled.
Bits 7- 4 - Reserved
Read/Write 0.
8.5.8 Line Status Register (LSR)
This register provides status information concerning the
data transfer. Bits 1 through 4 indicate Line status events.
These bits are sticky (accumulate the occurrence of error
conditions since the last time they were read). They are
cleared when one of the following events occurs:
q _{Hardware reset.}
q _{The receiver is soft-reset.}
q _{The LSR register is read.}
Upon reset this register assumes the value of 0x60h.
The bit definitions change depending upon the operation
mode of the module.
Bits 4 through 1 of the LSR are the error conditions that gen-
erate a Receiver Line Status interrupt whenever any of the
corresponding conditions are detected and that interrupt is
enabled.
The LSR is intended for read operations only. Writing to the
LSR is not permitted
76543210
Line Status
0 1 1 0 0 0 0 0 Reset
Register (LSR)
Bank 0,
Required
Offset 05h
RXDA
OE
PE
FE
BRK
TXRDY
TXEMP
ER_INF
FIGURE 8-14. LSR Register Bitmap
Bit 0 - Receiver Data Available (RXDA)
Set to 1 when the Receiver Holding Register is full.
If the FIFOs are enabled, this bit is set when at least one
character is in the RX_FIFO.
Cleared when the CPU reads all the data in the Holding
Register or in the RX_FIFO.
Bit 1 - Overrun Error (OE)
This bit is set to 1 as soon as an overrun condition is de-
tected by the receiver.
Cleared upon read.
With FIFOs Disabled:
An overrun occurs when a new character is completely
received into the receiver front-end section and the CPU
has not yet read the previous character in the receiver
holding register. The new character is discarded, and
the receiver holding register is not affected.
With FIFOs Enabled:
An overrun occurs when a new character is completely
received into the receiver front-end section and the
RX_FIFO is full. The new character is discarded, and
the RX_FIFO is not affected.
Bit 2 - Parity Error (PE)
This bit is set to 1 if the received data character does not
have the correct parity, even or odd as selected by the
parity control bits of the LCR register.
If the FIFOs are enabled, this error is associated with
the particular character in the FIFO that it applies to.
This error is revealed to the CPU when its associated
character is at the bottom of the RX_FIFO.
This bit is cleared upon read.
Bit 3 - Framing Error (FE)
This bit is set to 1 when the received data character
does not have a valid stop bit (i.e., the stop bit following
the last data bit or parity bit is a 0).
If the FIFOs are enabled, this Framing Error is associat-
ed with the particular character in the FIFO that it ap-
plies to. This error is revealed to the CPU when its
associated character is at the bottom of the RX_FIFO.
After a framing error is detected, the receiver will try to
resynchronize.
If the bit following the erroneous stop bit is 0, the receiv-
er assumes it to be a valid start bit and shifts in the new
character. If that bit is a 1, the receiver enters the idle
state and awaits the next start bit.
This bit is cleared upon read.
Bit 4 - Break Event Detected (BRK)
This bit is set to 1 when a break event is detected (i.e.
when a sequence of logic 0 bits, equal or longer than a
full character transmission, is received). If the FIFOs are
enabled, the break condition is associated with the par-
ticular character in the RX_FIFO to which it applies. In
this case, the BRK bit is set when the character reaches
the bottom of the RX_FIFO.
When a break event occurs, only one zero character is
transferred to the Receiver Holding Register or to the
RX_FIFO.
The next character transfer takes place after at least
one logic 1 bit is received followed by a valid start bit.
This bit is cleared upon read.
Bit 5 - Transmitter Ready (TXRDY)
This bit is set to 1 when the Transmitter Holding Regis-
ter or the TX_FIFO is empty.
It is cleared when a data character is written to the TXD
register.
Bit 6 - Transmitter Empty (TXEMP)
This bit is set to 1 when the Transmitter Holding Regis-
ter or the TX_FIFO is empty, and the transmitter front-
end is idle.
Bit 7 - Error in RX_FIFO (ER_INF)
This bit is set to a 1 if there is at least 1 framing error,
parity error or break indication in the RX_FIFO.
This bit is always 0 in the 16450 mode.
This bit is cleared upon read.
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