PC87317VUL Datasheet, PDF (55/272 Pages) National Semiconductor (TI) – PC87317VUL/PC97317VUL SuperI/O Plug and Play Compatible with ACPI Compliant Controller/Extender

Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Host PC
PC87317VUL
RTC
and
APC
Modules
V_DD Power
V_DD Sense
ONCTL
V_CCH Power
V_BAT Power
Power Supply Module
V_DD
External AC Power
V_CCH
Backup
Battery
FIGURE 4-2. PC87317VUL Power Supplies
Alarms
The timekeeping function may generate an alarm when the
current time reaches a stored alarm time. After each RTC
time update, the seconds, minutes, hours, day-of-month
and month storage registers are compared with their coun-
terparts in the alarm storage registers.
If equal, the alarm flag is set in Control Register C (CRC). If
the Alarm Interrupt Enable bit is set in Control Register B,
then setting the Alarm flag generates an RTC interrupt.
Any alarm register may be set to a “Don’t Care” state by set-
ting bits 7,6 to 11. This results in periodic alarm activation at
an increased rate whose period is that of the Don’t Care
register, e.g., if bits 7,6 of the hours register is set to 11(its
”Don’t care” value), the alarm will be activated every hour. If
the day-of-month register is set to its ”Don’t care” value, the
alarm will be activated daily at the time defined by the re-
maining alarm values.
The seconds, minutes and hours alarm registers are shared
with the wake-up function, and are located at indexes 01h,
03h and 05h of banks 0, 1 and 2, respectively. The day-of-
month alarm register is configurable. It may reside in bank
0 or bank 1. Upon first power-on, it resides in bank 1, Index
49h. The register is configured via the DADDR register in
bank 2. The month alarm register is also configurable and
may reside in bank 0 or bank 1. Upon first power-on, it re-
sides in bank 1, Index 4Ah. The register is configured via
the MADDR register in bank 2. For more details, see the
RTC and APC Registers.
The century register is configurable. It may reside in bank 0
or bank 1. Upon first power-on, it resides in bank 1, Index
48h. The register is configured via the CADDR register in
bank 2. For more details, see the RTC and APC Registers.
4.1.3 Power Management
The host PC and PC87317VUL power is supplied by the
system power supply voltage, V_DD. See FIGURE 4-2
"PC87317VUL Power Supplies".
A trickle voltage (V_CCH) from the external AC power supply
powers the RTC and APC under normal conditions. The
V_DD voltage reaches the RTC/APC as a sense signal, to de-
termine the presence or absence of a valid V_DD supply.
A battery backup voltage V_BAT maintains RTC/APC time-
keeping and backup memory storage when the V_CCH volt-
age is absent, due to power failure or disconnection of the
external AC input power supply.
The APC function produces the ONCTL signal, which con-
trols the V_DD power supply voltage. (See Section 4.4.1 "The
ONCTL Flip-Flop and Signal" on page 62.)
To ensure proper operation, a 500 mV differential is needed
between V_CCH and V_BAT.
See FIGURE 4-3 "Typical Battery Configuration". No exter-
nal diode is required to meet the UL standard, due to the in-
ternal serial resistor.
V_CCH
V_CCH
1µF
PC87317VUL
V_BAT
FIGURE 4-3. Typical Battery Configuration
System Bus Lockout
As the RTC switches to battery power, all input signals are
locked out so that the internal registers can not be modified
externally.
Power Up Detection
When system power is restored after a power failure, the
power failure lock condition continues for a delay of 62
msec (minimum) to 125 msec (maximum) after the RTC
switches from battery power to system power.
The power failure lock condition is switched off immediately
in the following situations:
q _{If the Divider Chain Control bits (DV2-0, bits 6-4 in Con-}
trol Register A) specify any mode other than 010, 100 or
011, all input signals are enabled immediately upon de-
tection of system voltage above that of the battery volt-
age.
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