PC87317VUL Datasheet, PDF (24/272 Pages) National Semiconductor (TI) – PC87317VUL/PC97317VUL SuperI/O Plug and Play Compatible with ACPI Compliant Controller/Extender

Signal/Pin Connection and Description
Signal/Pin Pin
Name Number
Module
I/O and
Group #
Function
WDATA
89
FDC
Output Write Data (FDC) – This output signal holds the write
Group 16 ^{precompensated serial data that is written to the selected floppy disk}
drive. Precompensation is software selectable.
WDO
156
Power Man- Output WATCHDOG Out – This output pin becomes low when a
agement _{Group 10} WATCHDOG time-out occurs. See Section 10.1.2 on page 218.This
pin is configured by bit 6 of the SuperI/O Configuration Register 2.
This signal is multiplexed with GPIO17.
WGATE
93
FDC
Output Write Gate (FDC) – This output signal enables the write circuitry of
Group 16 ^{the selected disk drive. WGATE is designed to prevent glitches during}
power up and power down. This prevents writing to the disk when
power is cycled.
WP
98
FDC
Input Write Protected – This input signal indicates that the disk in the
Group 1 ^{selected drive is write protected.}
WR
34
ISA-Bus
Input I/O Write – WR is an active low input signal that indicates a write
Group 1 ^{operation from the microprocessor to the controller.}
WRITE
112
Parallel Port Output Write Strobe – In EPP mode, this active low signal is a write strobe.
Group 23 This signal is multiplexed with STB. See TABLE 6-12 for more
information.
X1
50
Clock
Input Clock In – A TTL or CMOS compatible 14.31818MHz, 24 MHz or 48
Group 6 ^{MHz clock. When this pin is fed by the 14.31818MHz clock, the chip}
must be configured to work with the on-chip clock multiplier.See
Chapter 12 on page 230.
X1C
62
RTC
Input Crystal 1 Slow – Input signal to the internal Real-Time Clock (RTC)
crystal oscillator amplifier. Clock source is set by CFG0 during reset.
X2C
63
RTC
Output Crystal 2 Slow – Output signal from the internal Real-Time Clock
(RTC) crystal oscillator amplifier.
XD7,6,
XD1,0
XD5-2
78, 77
72, 71
76-73
X-Bus
X-Bus
I/O X-Bus Data – These bidirectional signals hold the data in the X Data
Group 9 ^{Buffer (XDB).}
XD7 is multiplexed with IRSL1 and ID1.
I/O _{XD6 is multiplexed with IRSL2, SELCS and GPIO21.}
Group 10 _{XD5-2 are multiplexed with GPIO27-24, respectively.}
XD1 is multiplexed with CS2.
XD0 is multiplexed with CS1/CSOUT-NSC-Test
See TABLE 1-2 on page 25.
XDCS
69
X-Bus
Input X-Bus Data Buffer (XDB) Chip Select – This signal enables and
Group 7 ^{disables the bidirectional XD7-0 data buffer signals.}
This signal is multiplexed with RING.
XDRD
70
X-Bus
Input X-Bus Data Buffer (XDB) Read Command – This signal controls the
Group 1 ^{direction of the bidirectional XD7-0 data buffer signals.}
This signal is multiplexed with ID3.
ZWS
31
ISA-Bus
Output Zero Wait State – When this open-drain output signal is activated
Group 22 ^{(driven low), it indicates that the access time can be shortened, i.e.,}
zero wait states.
ZWS is never activated (driven low) on access to SuperI/O chip
configuration registers (including during the Isolation state) or on
access to the parallel port in SPP or EPP 1.9 mode.
ZWS is always activated (driven low) on access to the parallel port in
ECP mode.
1. SCI is an internal signal used to send ACPI-relevant notifications to the host operating system.
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