PC87317VUL Datasheet, PDF (41/272 Pages) National Semiconductor (TI) – PC87317VUL/PC97317VUL SuperI/O Plug and Play Compatible with ACPI Compliant Controller/Extender

Configuration
2.6.2 Drive ID Register
This read/write register is reset by hardware to 00h. These
bits control bits 5 and 4 of the enhanced TDR register.
76543210
Drive ID Register,
0 0 0 0 0 0 0 0 Reset
Index F1h
Required
Drive 0 ID
Drive 1 ID
Reserved
FIGURE 2-11. Drive ID Register Bitmap
Bits 1,0 - Drive 0 ID
These bits are reflected on bits 5 and 4, respectively, of
the Tape Drive Register (TDR) of the FDC when drive 0
is accessed. See Section 5.3.4 "Tape Drive Register
(TDR)" on page 99.
Bits 3,2 - Drive 1 ID
These bits are reflected on bits 5 and 4, respectively, of
the TDR register of the FDC when drive 1 is accessed.
See Section 5.3.4 "Tape Drive Register (TDR)" on page
99.
Bits 7-4 - Reserved
2.7 PARALLEL PORT CONFIGURATION REGISTER
(LOGICAL DEVICE 4)
2.7.1 SuperI/O Parallel Port Configuration Register
This read/write register is reset by hardware to F2h. For nor-
mal operation and to maintain compatibility with future
chips, do not change bits 7 through 4.
SuperI/O Parallel Port
7 6 5 4 3 2 1 0 _{Configuration Register,}
1 1 1 1 0 0 1 0 Reset
Index F0h
Required
TRI-STATE Control
Clock Enable
Reserved
PP of PnP ISA Resource Data
Configuration Bits within the Parallel Port
Parallel Port Mode Select
FIGURE 2-12. SuperI/O Parallel Port Configuration
Register Bitmap
Bit 0 - TRI-STATE Control
When set, this bit causes the parallel port pins to be in
TRI-STATE (except IRQ and DMA pins) when the paral-
lel port is inactive (disabled). This bit is ORed with a bit
of the PMC1 register of logical device 8.
Bit 1 - Clock Enable
0: Parallel port clock disabled.
ECP modes and EPP time-out are not functional
when the logical device is active. Registers are
maintained.
1: Parallel port clock enabled.
All operation modes are functional when the logical
device is active. This bit is ANDed with a bit of the
PMC3 register of the power management device
(logical device 8).
Bit 2 - Reserved
Bit 3 - Reported Parallel Port of PnP ISA Resource Data
Report to the ISA PnP Resource Data the device identi-
fication.
0: ECP device.
1: SPP device.
Bit 4 - Configuration Bits within the Parallel Port
0: The registers at base (address) + 403h, base +
404h and base + 405h are not accessible (reads
and writes are ignored).
1: When ECP is selected by bits 7 through 5, the reg-
isters at base (address) + 403h, base + 404h and
base + 405h are accessible.
This option supports run-time configuration within
the Parallel Port address space. An 8-byte (and
1024-byte) aligned base address is required to ac-
cess these registers. See Chapter 6 "Parallel Port
(Logical Device 4)" on page 137 for details.
Bit 7-5 - Parallel Port Mode Select
Bit 5 is the LSB.
Selection of EPP 1.7 or 1.9 in ECP mode 4 is controlled
by bit 4 of the Control2 configuration register of the par-
allel port at offset 02h. See Section 6.5.17 "Control2
Register" on page 152.
000: SPP Compatible mode. PD7-0 are always output
signals.
001: SPP Extended mode. PD7-0 direction controlled
by software.
010:EPP 1.7 mode.
011:EPP 1.9mode.
100:ECP mode (IEEE1284 register set), with no sup-
port for EPP mode.
101:Reserved.
110:Reserved.
111:ECP mode (IEEE1284 register set), with EPP
mode selectable as mode 4.
41
www.national.com