PC87317VUL Datasheet, PDF (70/272 Pages) National Semiconductor (TI) – PC87317VUL/PC97317VUL SuperI/O Plug and Play Compatible with ACPI Compliant Controller/Extender

Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
The APC registers are not affected by Master Reset. They
are initialized to 0 only when power is applied for the first
time, i.e., application of one of the voltages V_BAT or V_CCH
when no previous voltage was present.
4.5.1 APC Control Register 1 (APCR1)
7654
0 0 00
321
000
0
0
Power-Up
Reset
Required
APC Control
Register 1
(APCR1)
Bank 2
Index 40h
Failsafe Timer Trigger Cmd.
Switch Off Delay Option
POR Edge or Level Select
Level POR Clear Command
MOAP
SOC
Fail-safe Timer Reset Command
Power Failure
FIGURE 4-14. APCR1 Register Bitmap
Bit 0 - Fail-safe Timer Trigger Command
This write-only bit returns 0 when read. Writing a 1 to
this bit resets the failsafe timer and triggers a 5 or 21
second countdown, as selected by bit 1 of this register.
0: Ignored.
1: 5 or 21 second failsafe countdown triggered.
Bit 1 - Switch Off Delay Option
0: 5 seconds.
1: 21 seconds.
Bit 2 - POR Edge or Level Select
0: Edge POR.
1: Level POR. Once POR is asserted, it remains as-
serted until cleared by Level POR Clear Command
(bit 3).
Bit 3 - Level POR Clear Command
This is a write-only non-sticky bit. Read returns 0.
0: Ignored.
1: POR output signal is deactivated.
Bit 4 - Mask ONCTL Activation if Power Fail (MOAP)
The function of this bit is enabled by extended wakeup
options settings in APCR6, bits 6 and 7.
0: When power returns and APCR6 bit 6 and 7 are
00, sets the system to the power state that existed
when power failed.
1: While the Power Failure bit (bit 7 of APCR1) is set,
mask ONCTL activation, except as a result of a
Switch On Event.
Bit 5 - Software Off Command (SOC)
This bit is write-only and non-sticky. Read returns 0.
0: Ignored.
1: ONCTL output signal is deactivated.
Bit 6 - Fail-safe Timer Reset Command
This bit is write-only and non-sticky. Read returns 0.
0: Ignored.
1: Fail-safe timer is stopped and reset.
Bit 7 - Power Failure
Set to 1 when RTC/APC switches from V_CCH to V_BAT.
Cleared to 0 by writing 1 to this bit. Writing 0 to this bit
has no effect.
4.5.2 APC Control Register 2 (APCR2)
76543210
APC Control
0
0
0
0
0
0
0
0
Power-Up
Reset
Register 2
(APCR2)
Required
Bank 2
Index 41h
TME
RSS
RPTDM
RE
R1E
R2E
SODE
Software On Command
FIGURE 4-15. APCR2 Register Bitmap
Bit 0 - Timer Match Enable (TME)
0: Pre-determined date or time event is ignored.
1: Match between the RTC and the pre-determined
date and time activates the ONCTL output signal.
See MOAP (bit 4) of APCR1 and APCR6 bit 6,7 for
an overriding case.
Bit 1 - RING Source Select (RSS)
0: RING source is RING/XDCS signal, regardless of
X-bus Data Buffer (XDB) select bit of SuperI/O
Configuration 1 register.
1: RING source is GPIO23/RING signal.
Bit 2 - RING Pulse or Train Detection Mode (RPTDM)
0: Detection of RING pulse falling edge.
1: Detection of RING pulse train above 16 Hz for 0.19
sec.
Bit 3 - RING Enable (RE)
0: RING input signal is ignored.
1: RING detection activates the ONCTL output signal,
unless it is overridden by the MOAP bit, bit 4 of the
APCR1 register and bits 6,7 0f APCR6.
Bit 4 - RI1 Enable (R1E)
0: RI1 input signal is ignored.
1: A high to low transition on the RI1 input pin acti-
vates the ONCTL output pin.
See MOAP (bit 4) of APCR1 and APCR6 bit 6,7 for
an overriding case.
Bit 5 - RI2 Enable (R2E)
0: RI2 input signal is ignored.
1: A high to low transition on the RI2 input pin acti-
vates the ONCTL output pin.
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