PC87317VUL Datasheet, PDF (107/272 Pages) National Semiconductor (TI) – PC87317VUL/PC97317VUL SuperI/O Plug and Play Compatible with ACPI Compliant Controller/Extender

The Digital Floppy Disk Controller (FDC) (Logical Device 3)
Even if drive polling is disabled, drive stepping and delayed
power-down occur in the drive polling phase. The controller
checks the status of each drive and, if necessary, it issues
a pulse on the STEP output signal with the DIR signal at the
appropriate logic level.
The controller also uses the drive polling phase to automat-
ically trigger power down. When the specified time that the
motor may be off expires, the controller waits 512 msec,
based on data transfer rates of 500 Kbps and 1 Mbps, be-
fore powering down, if this function is enabled via the
MODE command.
If a new command is issued while the FDC is in the drive
polling phase, the MSR does not indicate a ready status for
the next parameter byte until the polling sequence com-
pletes the loop. This can cause a delay between the first
and second bytes of up to 500 µsec at 250 Kbps.
5.5 THE RESULT PHASE STATUS REGISTERS
In the result phase of a command, result bytes that hold sta-
tus information are read from the Data Register (FIFO) at
offset 05h. These bytes are the result phase status regis-
ters.
The result phase status registers may only be read from the
Data Register (FIFO) during the result phase of certain
commands, unlike the Main Status Register (MSR), which
is a read only register that is always valid.
5.5.1 Result Phase Status Register 0 (ST0)
76543210
Result Phase Status
0 0 0 0 0 0 0 0 Reset ^{Register 0 (ST0)}
Required
Logical Drive Selected
(Execution Phase)
Head Selected (Execution Phase)
Not Used
Equipment Check
SEEK End
Interrupt Code
FIGURE 5-15. ST0 Result Phase Register Bitmap
Bits 1,0 - Logical Drive Selected
These two binary encoded bits indicate the logical drive
selected at the end of the execution phase.
The value of these bits is reflected in bits 1,0 of the SR3
register, described in Section 5.5.4 "Result Phase Sta-
tus Register 3 (ST3)" on page 109.
00: Drive 0 selected.
01: Drive 1 selected.
10: If four drives are supported, or drives 2 and 0 are
exchanged, drive 2 is selected.
11: If four drives are supported, drive 3 is selected.
Bit 2 - Head Selected
This bit indicates which side of the Floppy Disk Drive
(FDD) is selected. It reflects the status of the HDSEL
signal at the end of the execution phase.
The value of this bit is reflected in bit 2 of the ST3 regis-
ter, described in Section 5.5.4 "Result Phase Status
Register 3 (ST3)" on page 109.
0: Side 0 is selected.
1: Side 1 is selected.
Bit 3 - Not used.
This bit is not used and is always 0.
Bit 4 - Equipment Check
After a RECALIBRATE command, this bit indicates
whether the head of the selected drive was at track 0,
i.e., whether or not TRK0 was active. This information is
used during the SENSE INTERRUPT command.
0: Head was at track 0, i.e., a TRK0 pulse occurred
after a RECALIBRATE command.
1: Head was not at track 0, i.e., no TRK0 pulse oc-
curred after a RECALIBRATE command.
Bit 5 - SEEK End
This bit indicates whether or not a SEEK, RELATIVE
SEEK, or RECALIBRATE command was completed by
the controller. Used during a SENSE INTERRUPT com-
mand.
0: SEEK, RELATIVE SEEK, or RECALIBRATE com-
mand not completed by the controller.
1: SEEK, RELATIVE SEEK, or RECALIBRATE com-
mand was completed by the controller.
Bits 7,6 - Interrupt Code (IC)
These bits indicate the reason for an interrupt.
00: Normal termination of command.
01: Abnormal termination of command. Execution of
command was started, but was not successfully
completed.
10: Invalid command issued. Command issued was not
recognized as a valid command.
11: Internal drive ready status changed state during the
drive polling mode. This only occurs after a hard-
ware or software reset.
5.5.2 Result Phase Status Register 1 (ST1)
76543210
Result Phase Status
0 0 0 0 0 0 0 0 Reset ^{Register 1 (ST1)}
Required
Missing Address Mark
Drive Write Protected
Missing Data
Not Used
Overrun or Underrun
CRC Error
Not Used
End of Track
FIGURE 5-16. ST1 Result Phase Register Bitmap
107
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