PC87317VUL Datasheet, PDF (197/272 Pages) National Semiconductor (TI) – PC87317VUL/PC97317VUL SuperI/O Plug and Play Compatible with ACPI Compliant Controller/Extender

Enhanced Serial Port - UART1 (Logical Device 6)
q _{More than 64 µsec or four character times, whichever is}
greater, have elapsed since the last byte was read from
the RX_FIFO by the CPU.
8.4 AUTOMATIC FALLBACK TO A NON-EXTENDED
UART MODE
The automatic fallback feature supports existing legacy
software packages that use the 16550 UART by automati-
cally turning off any Extended mode features and switches
the UART to Non-Extended mode when either of the LB-
GD(L) or LBGD(H) ports in bank 1 is read from or written to
by the CPU.
This eliminates the need for user intervention prior to run-
ning a legacy program.
In order to avoid spurious fallbacks, alternate baud rate reg-
isters are provided in bank 2. Any program designed to take
advantage of the UART’s extended features, should not use
LBGD(L) and LBGD(H) to change the baud rate. It should
use the BGD(L) and BGD(H) registers instead. Access to
these ports will not cause fallback.
Fallback can occur in any mode. In Extended UART mode,
fallback is always enabled. In this case, when a fallback oc-
curs, the following happens:
q _{Transmission and Reception FIFOs switch to 16 levels.}
q _{A value of 13 is selected for the baud rate generator}
prescaler
q _{The BTEST and ETDLBK bits in the EXCR1 register}
are cleared.
q _{UART mode is selected.}
q _{A switch to a Non-Extended UART mode occurs.}
When a fallback occurs in a Non-Extended UART mode, the
last two of the above actions do not take place.
Fallback from a Non-Extended mode can be disabled by
setting the LOCK bit in register EXCR2. When LOCK is set
to 1 and the UART is in a Non-Extended mode, two scratch
registers overlaid with LBGD(L) and LBGD(H) are enabled.
Any attempted CPU access of LBGD(L) and LBGD(H) ac-
cesses the scratch registers, and the baud rate setting is not
affected. This feature allows existing legacy programs to
run faster than 115.2 Kbps.
8.4.1 Transmission Deferral
This feature allows software to send high-speed data in Pro-
grammed Input/Output (PIO) mode without the risk of gen-
erating a transmitter underrun.
Transmission deferral is available only in Extended mode
and when the TX_FIFO is enabled. When transmission de-
ferral is enabled (TX_DFR bit in the MCR register set to 1)
and the transmitter becomes empty, an internal flag is set
and locks the transmitter. If the CPU now writes data into
the TX_FIFO, the transmitter does not start sending the
data until the TX_FIFO level reaches 14 at which time the
internal flag is cleared. The internal flag is also cleared and
the transmitter starts transmitting when a time-out condition
is reached. This prevents some bytes from being in the
TX_FIFO indefinitely if the threshold is not reached.
The time-out mechanism is implemented by a timer that is
enabled when the internal flag is set and there is at least
one byte in the TX_FIFO. Whenever a byte is loaded into
the TX_FIFO the timer gets reloaded with the initial value. If
no bytes are loaded for a 64-µsec time, the timer times out
and the internal flag is cleared, thus enabling the transmit-
ter.
8.5 BANK 0 – GLOBAL CONTROL AND STATUS
REGISTERS
In the Non-Extended modes of operation, bank 0 is compat-
ible with both the 16450 and the 16550. Upon reset, this
module defaults to the 16450 mode. In the Extended mode,
all the Registers (except RXD/ TXD) offer additional fea-
tures.
TABLE 8-2. Bank 0 Serial Controller Base Registers
Offset
Register
Name
Description
00h RXD/ Receiver Data Port/ Transmitter Data
TXD
Port
01h
IER
Interrupt Enable Register
02h EIR/
FCR
Event Identification Register/
FIFO Control Register
03h LCR/
BSR
Line Control Register/
Bank Select Register
04h MCR
Modem Control Register
05h LSR
Line Status Register
06h MSR
Modem Status Register
07h SCR/
Scratch Register/
ASCR Auxiliary Status and Control Register
8.5.1 Receiver Data Port (RXD) or the Transmitter
Data Port (TXD)
These ports share the same address.
RXD is accessed during CPU read cycles. It is used to read
data from the Receiver Holding Register when the FIFOs
are disabled, or from the bottom of the RX_FIFO when the
FIFOs are enabled. See Figure 8-3.
Receiver Data Port (RXD)
76543210
Receiver Data
Reset
Port (RXD)
Bank 0,
Required
Offset 00h
Received Data
FIGURE 8-3. RXD Register Bitmap
Bits 7-0 - Received Data
Used to access the Receiver Holding Register when the
FIFOs are disabled, or the bottom of the RX_FIFO when
the FIFOs are enabled.
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