PC87317VUL Datasheet, PDF (123/272 Pages) National Semiconductor (TI) – PC87317VUL/PC97317VUL SuperI/O Plug and Play Compatible with ACPI Compliant Controller/Extender

0: Single track. The controller stops at the last sector
of side 0.
1: Multiple tracks. the controller continues to side 1 af-
ter reaching the last sector of side 0.
Second Command Phase Byte
Bits 1,0 - Logical Drive Select (DS1,0)
These bits indicate which logical drive is active. See
“Bits 1,0 - Logical Drive Select (DS1,0)” on page 116.
00: Drive 0 is selected. (Default)
01: Drive 1 is selected.
10: If four drives are supported, or drives 2 and 0 are
exchanged, drive 2 is selected.
11: If four drives are supported, drive 3 is selected.
Bit 2 - Head (HD)
This bit indicates which side of the Floppy Disk Drive
(FDD) is selected by the head. Its value is the inverse of
the HDSEL disk interface output signal.See “Bit 2 -
Head Select (HD)” on page 116.
0: HDSEL is not active, i.e., the head of the FDD se-
lects side 0. (Default)
1: HDSEL is active, i.e., the FDD head selects side 1.
Bit 7 - Implied Seek (IPS)
This bit indicates whether or not an implied seek should
be performed. See also, “Bit 5 - Implied Seek (IPS)” on
page 119.
A software reset clears this bit to its default value of 0.
0: No implied seek operations. (Default)
1: The controller performs seek and sense interrupt
operations before executing the command.
Third Command Phase Byte - Track Number
The value in this byte specifies the number of the track
to read.
Fourth Command Phase Byte - Head Number
The value in this byte specifies head to use.
Fifth Command Phase Byte - Sector Number
The value in this byte specifies the sector to read.
Sixth Command Phase Byte - Bytes-Per-Sector Code
This byte contains a code in hexadecimal format that in-
dicates the number of bytes in a data field. TABLE 5-11
"Bytes per Sector Codes" on page 116 indicates the
number of bytes that corresponds to each code.
Seventh Command Phase Byte - End of Track (EOT)
Sector Number
This byte specifies the number of the sector at the End
Of the Track (EOT).
Eighth Command Phase Byte - Bytes Between Sectors
- Gap 3
The value in this byte specifies how many bytes there
are between sectors. See “Fifth Command Phase Byte
- Bytes in Gap 3” on page 117.
Ninth Command Phase Byte - Data Length (Obsolete)
The value in this byte is ignored and must be set to FFh.
Execution Phase
In this phase, data read from the disk drive is transferred to
the system via DMA or non-DMA modes. See Section 5.4.2
"Execution Phase" on page 104.
The controller looks for the track number specified in the
third command phase byte. If implied seeks are enabled,
the controller also performs all operations of a SENSE IN-
TERRUPT command and of a SEEK command (without is-
suing these commands). Then, the controller waits the head
settle time. See bits 3-0 of the fourth command phase byte
of the MODE command in “Bits 3-0 - Head Settle Factor” on
page 120.
The controller then starts the data separator and waits for
the data separator to find the address field of the next sec-
tor. The controller compares the ID information (track num-
ber, head number, sector number, bytes-per-sector code) in
that address field with the corresponding information in the
command phase bytes of the READ DATA command.
If the contents of the bytes do not match, then the controller
waits for the data separator to find the address field of the
next sector. The process is repeated until a match or an
error occurs.
Possible errors, the conditions that may have caused them
and the actions that result are:
q _{The microprocessor aborted the command by writing to}
the FIFO.
If there is no disk in the drive, the controller gets stuck.
The microprocessor must then write a byte to the FIFO
to advance the controller to the result phase.
q _{Two pulses of the INDEX signal were detected since the}
search began, and no valid ID was found.
If the track address differs, either the Wrong Track bit
(bit 4) or the Bad Track bit (bit 1) (if the track address is
FFh) is set in result phase Status register 2 (ST2). See
Section 5.5.3 "Result Phase Status Register 2 (ST2)" on
page 108.
If the head number, sector number or bytes-per-sector
code did not match, the Missing Data bit (bit 2) is set in
result phase Status register 1 (ST1).
If the Address Mark (AM) was not found, the Missing Ad-
dress Mark bit (bit 0) is set in ST1.
Section 5.5.2 "Result Phase Status Register 1 (ST1)" on
page 107 describes the bits of ST1.
q _{A CRC error was detected in the address field. In this}
case the CRC Error bit (bit 5) is set in ST1.
Once the address field of the desired sector is found, the
controller waits for the data separator to find the data field
for that sector.
If the data field (normal or deleted) is not found within the
expected time, the controller terminates the operation, en-
ters the result phase and sets bit 0 (Missing Address Mark)
in ST1.
If a deleted data mark is found, and Skip (SK) control is set
to 1 in the opcode command phase byte, the controller skips
this sector and searches for the next sector address field as
described above. The effect of Skip Control (SK) on the
READ DATA command is summarized in TABLE 5-17
"Skip Control Effect on READ DATA Command".
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